分析ni官方培训lesson modular programming

1、Lesson 10Modular ProgrammingReview of SubVIsUsing SubVIs on the FPGAReentrancy and Non-reentrancy in FPGAUsing Name Controls and ConstantsTesting FPGA SubVIsLabVIEW FPGA IPNetA. Review Understanding ModularityModularity defines the degree to which a program is composed of discrete modules such that

2、a change to one module has minimal impact on other modulesModules in LabVIEW are called subVIsReview SubVIs A VI within another VI is a subVIThe upper right corner of the front panel and block diagram displays the icon for the VIThis icon identifies the VI when you place the VI on the block diagramR

3、eview - Icon and Connector PaneAfter you build a VI, build the icon and the connector pane so you can use the VI as a subVIThe icon and connector pane correspond to the function prototype in text-based programming languagesEvery VI displays an icon in the upper-right corner of the front panel and bl

4、ock diagram windowsAn icon is a graphical representation of a VIIf you use a VI as a subVI, the icon identifies the subVI on the block diagram of the VIReview - Icon and Connector Pane Setting up the Connector PaneRight-click the icon in the upper right corner of the front panel and select Show Conn

5、ectorEach rectangle on the connector pane represents a terminalUse the terminals to assign inputs and outputsSelect a different pattern by right-clicking the connector pane and selecting Patterns from the shortcut menuReview - Using SubVIs Terminal SettingBold: Required terminalPlain: mended termina

6、lsDimmed: Optional terminalsReview - Using SubVIs Section to SubVITo convert a section of a VI into a subVI:Use the Positioning tool to select the section of the block diagram you want to reuse Select EditCreate SubVIB. Using SubVIs on the FPGAYou can run only one top-level FPGA VIYou can use multip

7、le VIs on the FPGA by placing subVIs on the block diagram of the top-level FPGA VIPlacing large controls and indicators on the front panel of a subVI is acceptableSubVI controls and indicators are not exposed to the hostC. Reentrancy and Non-reentrancy in FPGAReentrant FPGA SubVI ConfigurationDefaul

8、t configuration of VIs created under an FPGA targetMultiple calls to the same subVI run in parallel using separate FPGA resourcesReentrant FPGA SubVIEach instance of the reentrant FPGA subVI on the block diagram es a separate hardware resourceNonreentrant FPGA SubVISingle instance shared among multi

9、ple callersEach call to the subVI waits until the previous call endsDoes not allow parallel executionNonreentrant FPGA SubVIOnly a single copy of the nonreentrant FPGA subVI es hardware and all callers share the hardware resourceReentrancy and Non-reentrancy in FPGATradeoffsReentrant is the default

10、VI Type for FPGA VIsComparisonReentrant SubVINonreentrant SubVIFPGA Resources for VI LogicSeparate for each instantiationSingle set for all instantiationsParallel ExecutionYesNoOptimized forSpeedSize (Typically)Use in Single-Cycle Timed LoopYesOnly if called from one placeD. Using Name Controls and

11、ConstantsUsing FPGA Name Controls in SubVIsFPGA I/O controlFPGA Clock controlMemory controlFIFO controlFPGA I/O ControlPasses FPGA I/O items to subVIsCreate VIs that can be used as reentrant subVIs with configurable I/O itemsFPGA I/O ControlPlace FPGA I/O Node in subVIRight-click FPGA I/O In input a

12、nd select CreateControlWire the FPGA I/O control to the subVI connector paneFPGA Clock ControlPass FPGA Clocks to subVIsFPGA Clock ControlPlace SCTL in subVIRight-click the Source Name input of an SCTL and select CreateControl.Wire the clock control to the subVI connector paneFPGA Memory ControlPass

13、 memory items to subVIsRight-click the Memory In input of a Memory Method node and select CreateControlWire the memory control to the subVI connector paneFPGA FIFO ControlPass FPGA FIFO items to subVIsRight-click the FIFO In input of a FIFO Method node and select CreateControlWire the FIFO control t

14、o the subVI connector paneFPGA Control RestrictionsYou cannot change the value of FPGA controls and indicators while an FPGA VI runs on the development computer or when using Interactive Front Panel communicationYou cannot access FPGA controls and indicators from the FPGA InterfaceYou can bundle FPG

15、A controls into clusters with other FPGA controls, but not with other data typesE. Testing FGPA SubVIsTest subVIs as top-level VIsExecute on development computerExecute on FPGA targetF. LabVIEW FPGA IPNetLabVIEW FPGA IPNetResource for downloading and sharing LabVIEW FPGA functions and intellectual p

16、ropertyAcquire IP needed for your applicationDownload examples to learn programming techniquesShare your LabVIEW FPGA IPExercise 10-1: Creating an FPGA SubVICreate an FPGA subVI and call it from an FPGA main VI.Exercise 10-1: Creating an FPGA SubVI If you needed to monitor additional AI channels and

17、 control additional DIO lines, how would you change your code? How would the behavior of this application change if you changed the subVI from reentrant to nonreentrant?SummaryQuizTrue or False? Controls and indicators on an FPGA subVI are exposed to the host VI.SummaryQuiz AnswerTrue or False? Cont

18、rols and indicators on an FPGA subVI are exposed to the host VI.False.SummaryQuizWhich of the following are true for reentrant subVIs in LabVIEW FPGA?Default configuration of VIs created under an FPGA targetEach instance on the block diagram es a separate hardware resourceOptimized for FPGA sizeEach

19、 call to the subVI waits until the previous call endsMultiple calls to the same subVI run in parallelSummaryQuiz AnswersWhich of the following are true for reentrant subVIs in LabVIEW FPGA?Default configuration of VIs created under an FPGA targetEach instance on the block diagram es a separate hardw

20、are resourceOptimized for FPGA sizeEach call to the subVI waits until the previous call endsMultiple calls to the same subVI run in parallelSummaryQuizWhich of the following are FPGA name controls that can be passed into FPGA subVIs?FPGA I/O controlFPGA Clock controlFPGA FIFO controlFPGA Memory cont

21、rolSummaryQuiz AnswersWhich of the following are FPGA name controls that can be passed into FPGA subVIs?FPGA I/O controlFPGA Clock controlFPGA FIFO controlFPGA Memory controlContinuing Your LabVIEW EducationInstructor Led TrainingLabVIEW Real-Time 1LabVIEW Real-Time 2LabVIEW PerformanceContinuing Yo

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