cypress68013开发cy7c68013学习入门必读implementing

1、Implementing FIFO (multiple) TranionsA fully working external FIFO exle using GPIF Single tranions has already been discussed, butthe bandwidth achieved is miniscule. This is because there is a lot of firmware overhead involved inlaunching GPIF Single tranions. With GPIF FIFO tranions, the GPIF engi

2、ne directly handlesbursts of data, so a higher bandwidth over the physicalerface is achievable.GPIF Single tranions 已经被，但是能达到的带宽很小，因为在进行 GPIF Single tranions 中有很大一部分 firmware 参与。GPIF FIFO tran达到一个 higher bandwidthions，GPIF engine 直接处理数据的快速传输，因此在物理界面能roducing the Flow Se Feature of the GPIF介绍 GPIF 的

3、Flow Se 功能：In order to efficiently handursts of data and meet burst acs timing to the external FIFO, the flowse feature of the GPIF was utilized for the FIFO tranion exle.为了更有效处理突发数据，适应外部 FIFO 的 burst acs 时序，FIFO tranion exle 里面利用了 GPIF的 flow sThe flow se 功能e feature makes its debut（首次使用）he FX2 GPIF

4、 and is a mechanismt allows theGPIF to efficiently throttle data on and off the bus by using an independent set of RDYn logic (flow logic)t is separate from the decipoRDYn logic.flow se 是这样一个装置：让 GPIF 更有效进行总线数据的开关流量控制，通过使用一个从点的 RDYn 逻辑中分离出来的 RDYn logic (flow logic)独立集。Since the flow se feature is an

5、 advanced mode of the GPIF, not every application will need to use theflow se.因为 flow se 是 GPIF 的一种高级模式，不是所有的应用都需要使用 flow se。However, handling bursts of dao and from an external FIFO shows the simplest application of the flowse.然而，处理在外部 FIFO 之间传输的突发数据展示了最简单的 flow se 应用。eration of UDMA waveforms for

6、the FX2One very advanced application of the flow smass storage reference design firmware.e is一个非常高级的 flow se 应用是为 FX2 大容量参考设计固件程序产生 UDMA 波形。In any GPIF waveform, there can only be one flow s(S0S6).e, but it can be any of the available non-idle ses在任何 GPIF 波形，可以只有一个 flow se，但是也可以是任何可用的 non-idle ses (

7、S0S6)。The flow se behavior is controlled by a set of registerst are specific to the flow se feature (seethe FX2 Technical Reference Manual for flow se register details).flow se 行为被一组寄存器控制，在 FX2 参考手册中描述 flow se 寄存器细节。One can think of the flow se as being “orthogonal” to one of the GPIF waveforms ses,

8、 but it is stillthe regular decipologict is responsible for determining when the flow se should be exitedand the normal GPIF waveform behavior continues.可以认为 flow se 是 GPIF 波形其中之一的正交，但是它仍然是常规点逻辑当 flow se 应该被结束，普通 GPIF 波形行为持续时？Anothroperty of the flow se ist it can be programmed to perform a differen

9、t set of CTLx logicn what is describedhe GPIF waveform descriptors themselves.另一个 flow se 属性是它能被编程提供一个不同的被描述在 GPIF 波形描述符中的 CTLx 逻辑。This brings the level of autonomy to another notch.这种方法了 GPIF 的自控制能力。The idea behind the GPIF FIFO Read and Write descriptor programming is to have the read and writecon

10、trol lines assert for the duration of the tranof IFCLK.ion, thereby allowing dao be moved on every edge这种方法因此允许在每个 IFCLK 边沿进行数据传输，？Therefore, a 16-biterface running at 48 MHz would yield an effective burst data rate of 96 MB/s over theGPIFerface.因此运行在 48M 的 16 位接口能够在 GPIF 接口得到 96M/s 的突发数据传输速率。The ma

11、in difference betn this FIFO tranion verand the single tranion veristwaveforms 2 and 3 are used (FIFORd and FIFOWr waveforms, respectively) instead of waveforms 0 and1.FIFO 传输和 single 传输的主要不同是 FIFORd2 and FIFOWr3RDY5 is used as the GPIF tranion count (GPIF TC)ernal expiration flag (TCXpire).RDY5 被用作

12、 GPIF 的传输计数器到达标志 TCXpireThe GPIF TC is what is usedhe waveforms decipologic to determine when to exit out of theflow se and terminate the waveform.GPIF TC 被用在波形的点去决定什么时候退出 flow se 和中止波形。Figure 16 shows the set-up of the block diagram andthe naming conventions of the CTLx and RDYnsignals (same as the

13、 single tranion exle).Figure 17 below shows waveform 3, which characterizes the behavior of the FIFO Write waveform.his FIFO Write waveform (waveform 3) we seet S0 isriod of inactivity, followed by S1 which isdesignated as the flow se. The decipologic in S1 looks at the GPIF TC to determine when tot

14、erminate the waveform by branching to the IDLE se. As previously mentioned, the flow logic in S1then takes over to throttle data on and off the bus and manipulate the CTLx lines. The flow se registersare set up by selecting the various flow strace.e parameters, acsed by right clicking on the S1 seIn

15、 order to set up the flow se for both FIFO reads and writes, a set of global GPIF and flow seregisters are GPIF Designer.(Note: The FlowSinitialized. The values are taken from a FlowSes36 array in gpif.c, generated byes array, in GPIF.c, could be re-declared as FlowSes49, for simplicity. The9 elemen

16、ts contain the FlowSe register values for waveform 0. The next 9 elements contain theFlowSFlowSe register values for waveform 1, etc. Therefore, FlowSes21.)es19 is the same element asEP2GPIFSEL = 0 x01; / For EP2OUT, GPIF uses EF flagSYNCDELAY;EP6GPIFSEL = 0 x02; / For EP6IN, GPIF useslagSYNCDELAY;/

17、 global flowse register initializationsFLOWLOGIC = FlowS SYNCDELAY; FLOWSTB = FlowSSYNCDELAY;es19; / 0011 0110b - LFUNC1:0 = 00 (A AND B), TERMA/B2:0=110 (FIFO Flag)es22; / 0000 0100b - MSTB2:0 = 100 (CTL4), not used as strobeGPIFHOLDAMOUNT = FlowSSYNCDELAY;es26; / hold data for one half clock (10ns

18、) aming 48MHz IFCLKFLOWSTBEDGE = FlowSSYNCDELAY;es24; / move data on both edges of clockFLOWSTBHPERIOD = FlowSSYNCDELAY;es25; / 20.83ns half periodThe set-up icht when FIFO Write tranions are launched from EP2OUT, the GPIF uses EP2sempty flag (EF) as the FIFO Flag, and when FIFO Read tranuses EP6s f

19、ull flag (FF) as the FIFO Flag.ions are launchedo EP6IN, the GPIFSubsequently, the flow logic is set up to use the FIFO Flag to throttle data on and off the bus, so the flowse mechanism actually uses EP2EF and EP6FF sus to know when to keep writing to the data bus orkeep reading from the data bus, r

20、espectively.Although CTL4 (unused) is not usedhe application, we take advantage of the factt the flow secan use any of the CTLx lines as a data strobe. At a 48-MHz IFCLK, CTL4 is toggled at a half period of20.83 ns. Since the flow se is also programmed to move data on both edges of the data strobe,

21、thisallows us to nicely align the data values with the rising edge of IFCLK and achieve a 96-MB/s burst rateover the physicalerface. Notet although CTL4 is not physically exed on the 56-pin package, theflow se logic can still be set up to use it as a data strobe.Lets also examine the flow se registe

22、r set-upt is specific to FIFO Writes:void Setup_FLOWSE_Write ( void )FLOWSE = FlowSes18; / 1000 0001b - FSE=1, FS2:0=001SYNCDELAY; FLOWEQ0CTL = FlowS SYNCDELAY; FLOWEQ1CTL = FlowS SYNCDELAY;es20; / CTL0 = 0 when flow condition equals zero (data flows)es21; / CTL0 = 1 when flow condition equals one (

23、data does not flow)Here we designate S1 to be the flow se and define the se of CTL0 when the flow condition equalszero (data flows) and when the flow condition equals one (data does not flow). Remembert the seof the flow condition is determined by the se of EP2EF. So when the EP2 FIFO contains data

24、(EP2 isnot empty) the flow condition equals zero, the flow sis placed on FD15:0.e drops CTL0 LOW (WEN# is asserted), and dataFigure 18 below shows waveform 2, which characterizes the behavior of the FIFO Read waveform.Figure 18. FIFO Read waveform in GPIF Designerhis FIFO Read waveform (waveform 2)

25、S0 isriod of inactivity, then S1 and S2 sets up the “frontporch” of the burst transfer, followed by S3 which is designated as the flow se.在这个 FIFO Read waveform (waveform 2),S0 是一个周期，S1 和 S2 设置为突发传输的前沿，跟随的 S3设计为 flow se。The decipologic in S3 looks at the GPIF TC to determine when to terminate the wa

26、veform bybranching to the IDLE se. As previously mentioned, the flow logic in S3 then takes over to throttle datareads from the bus and manipulate the CTLx lines.Lets examine the flow se register set-upt is specific to FIFO Reads:void Setup_FLOWSE_Read ( void )FLOWSE = FlowSes27; / 1000 0011b - FSE=

27、1, FS2:0=003SYNCDELAY; FLOWEQ0CTL = FlowS(data flows) SYNCDELAY; FLOWEQ1CTL = FlowSflow) SYNCDELAY;es29; / CTL1/CTL2 = 0 when flow condition equalszeroes30; / CTL1/CTL2 = 1 when flow condition equals one (data does notHere we designate S3 to be the flow se and define the se of CTL1 and CTL2 when the

28、 flow conditionequals zero (data flows) and when the flow condition equals one (data does not flow).这儿CTL1指定了 S3 作为 flow s和 CTL2 的状态e，同时定义了当 flow 条件0（数据）和 flow 条件1（数据不）时Remembert the se of the flow condition is determined by the se of EP6FF. So when the EP6 FIFOhas room for data (EP6 is not full) th

29、e flow condition equals zero, the flow sLOW (REN and OE are asserted), and data is read from FD15:0.e drops CTL1 and CTL2记住 se 的条件被 EP6FF 的状态决定，因此当 EP6 FIFO 有数据空间(EP6 is not full)，flow condition0，the flow se 拉低 CTL1 和 CTL2（REN 和 OE 被设定），数据从 FD15:0被读出。Since there is a different flow se register set-u

30、p for FIFO read and write operations, the firmware has tocall Setup_FLOWSE_Read() before launching a GPIF FIFO read tranion, and callion.Setup_FLOWSE_Write() before launching a GPIF FIFO write tran因为 FIFO read and write 操作有不同的 flow se 寄存器设置，在进行 GPIF FIFO read 传输必须调用Setup_FLOWSE_Read()，在进行 GPIF FIFO

31、write 传输必须调用 Setup_FLOWSE_Write()。Nowt you understand how the GPIF FIFO read and write waveforms were programmed and set up, thefirmware programming fPIF FIFO tranions can be discussed.现在你已经理解了如何编程和设置 GPIF FIFO read and write 波形，下面GPIF FIFO 传输的固件编程。FIFO Tranion Firmwareoving from GPIF Single tranion

32、s to GPIF FIFO tranions, the only major differencereallyshe TD_Poll() code.最主要的区别是在 TD_Poll()The basic underlying architecture of the exle remains the same.his section, the basic principles of launching a FIFO tranion areroduced. Followingtis a discusof the TD_Poll() codet triggers the GPIF FIFO tra

33、nions.Triggering GPIF FIFO TranionsFor triggering GPIF FIFO tran(TC).ions, we reiterate the concept of the GPIF tranion count为了触发 GPIF FIFO tranions，重申 GPIF 传输计数器（TC）的概念。ogous to the Tcount variablehe single tranion exle, the TC is a value the GPIFengine uses to determine how many times to go throug

34、h a FIFO waveform.类似 single tran行了多少次。ion 例子里面的 Tcount 变量，TC 是 GPIF engine 用来测定 FIFO waveform 被执For exle, if the user wished to burst out 512 bytes of data from the EP2OUT endpo, the TCvalue would be set to 512 (for byte wide operation) or 256 (for word wide operation).举例说明，如果用户想从 EP2OUT 端点快速突发输出 51

35、2 字节数据，TC 设置为 512（字节宽度），256（字宽度）。The GPIF engine then decrements the TC value on every push or pop of the FIFO.GPIF engine 在每次 push or pop FIFO 时，TC 值每次递减。When the TC value reaches zero, the waveform is complete (a waveform completion is signifiedby the GPIFDONE being sethe GPIFIDLECS register).当 TC

36、=0，波形完成（波形完成被 GPIFIDLECS 寄存器的 GPIFDONE 指示）A decipose can use the TC value as ane.ernal flag to determine whether or not tobranch to the IDLE s一个点状态能够使用 TC 值作为flag 去决定是否跳转到 IDLE 状态。GPIFREADYCFG.5 must be set to allow the GPIF engine to use the RDY5 signal as anexpiration flag.ernal TCGPIFREADYCFG.5 必

37、须被设置去允许 GPIF engine 去使用 RDY5 信号作为TC 到达预期标志。The act of triggering a GPIF FIFO tranion iually very simple. Writing to the R/W bition.heGPIFTRIG register sets the direction of the tran触发一次 GPIF FIFO 传输的操作非常简单，写 GPIFTRIG 寄存器的 R/W 位设置传输方向。If R/W=1, a FIFO Read tranion gets triggered when acsing the GPIFT

38、RIG register. If R/W=0,a FIFO Write tranR/W=1 -FIFO 读ion get triggered instead.R/W=0FIFO 写For exle, to trigger a GPIF FIFO Read tranion to EP6IN use the following line of codeGPIFTRIG = GPIFTRIGRD | GPIF_EP6; / launch GPIF FIFO Read tranion to EP6INTo trigger a GPIF FIFO Write tranion from EP2OUT us

39、e the following line of code:GPIFTRIG = GPIF_EP2; / launch GPIF FIFO Write tranion from EP2OUTGPIFTRIGRD, GPIF_EP6, and GPIF_EP2 are bit masks to set the appropriate bitshe GPIFTRIG register. or 3 (in order of theion. Source or sinkBy setting the EP1:0 bits in the GPIFTRIG register to valid optionso

40、f 0,1,2,he tran.endpos 2,4,6, and 8), this specifies which endposhould be useddirection is impd by whetherpois an IN or and OUT endpoTD_Init( )The initialization codeD_Init( ) remains pretty much the same as the single tranion ver. Themain differenin the setup of the FIFOCFG registers. Toize the USB

41、 2.0 bandwidth, thet the bits 1 and 0 of the REVCTLendpos are placedo auto mode (AUTOOUT/AUTOIN=1). Noteregister are not set. Therefore, it is nesary toset AUTOOUT=0, then set AUTOOUT=1. The FX2needs to see a 0 to 1 transition of the AUTOOUT bit to automatically armpobuffers.有必要首先去设置 AUTOOUT=0，然后设置

42、AUTOOUT=1，为了自动处理端点缓冲区，FX2 需要看见 AUTOOUT位的到 1 的变化。/ set the CPU clock to 48MHzCPUCS = (CPUCS & bmCLKSPD) | bmCLKSPD1); SYNCDELAY;EP2CFG = 0 xA0; / EP2OUT, bulk, size 512, 4x buffered SYNCDELAY;EP6CFG = 0 xE0; / EP6IN, bulk, size 512, 4x bufferedSYNCDELAY;FIFORESET = 0 x80; / set NAKALL bit to NAK all

43、transfers from host SYNCDELAY;FIFORESET = 0 x02; / reset EP2 FIFO SYNCDELAY;FIFORESET = 0 x06; / reset EP6 FIFO SYNCDELAY;FIFORESET = 0 x00; / clear NAKALL bit to resume normal operationSYNCDELAY;EP2FIFOCFG = 0 x01; SYNCDELAY;EP2FIFOCFG = 0 x11; / auto out mode, disable PKTEND zero length send, word

44、 opsSYNCDELAY;EP6FIFOCFG = 0 x09; / autoSYNCDELAY;ode, disable PKTEND zero length send, word opsGpifInit (); / initialize GPIF registers/ reset the external FIFOOEA |= 0 x04; / turn on PA2 as output pin IOA |= 0 x04; / pull PA2 high initiallyIOA &= 0 xFB / bring PA2 lowEZUSB_Delay (1); / keep PA2 lo

45、w for 1ms, more IOA |= 0 x04; / bring PA2 highn enough timeTD_Poll()EP2 OUT-EP6INndling code does is it checks to see if the GPIF is IDLE. If so, it checks to see ifThething the OUthere is at least a packet in the peripheralfor EP2. Since EP2 is placedo auto mode, thefirmware does not need to check

46、if the host sent a USB packet. The USB packets are automaticallycommitted to be used by the GPIF engine. Therefore, the firmwares job is to check ifeast one packethas been committed to the peripheral.首先通过代码的操作检查GPIF是否为IDLE。检查在外设EP2 中是否至少有一个数据包。Since EP2 is placedoauto mode,固件不需要检查主机是否发送一个 USB 包。这个 U

47、SB 数据包被用于 GPIF 启动。因此，固件的工作是去检查至少有一个数据包被传送到外部 damain 中Then, if the external FIFO is not full, the TC value is setup for word wide operation (256). The TC value is a32-bit register field, but for this application only the lower 16-bit fields are nesary. Since each GPIFerface, the number ofFIFO Write t

48、ranion sends 512 bytes to the external FIFO over a 16-bittranions is always half the number of bytes actually contained within the endpobuffer. Theappropriate TC value is setup for either high speed or full speed operation.如果 FIFO 不是满的， TC 的值将会顺着数据的字符的宽度来调整。TC 的值是个 32 位的寄存器字域，但是根据这个运用，只有 16 位的被运用到。自

49、从每个 GPIF FIFO 以 512 的速度来写向外部 FIFO16 位数。处理事务的数量一直是字节的一半 ，它实际包含了端点缓冲部分。合适的 TC 值可以校正到高速或全速The appropriate flow se registers are then setup for the FIFO Write tranion, and a write to theGPIFTRIG register with the appropriate bits triggers the tranion from EP2OUT. The code then waitsfor the tranion to co

50、mplete before exiting out of the if nest.The appropriate flow se registers 调整 FIFO 写事务，一个写向 GPIFTRIF 寄存器的?.在 exiting out if嵌套之前，是等待事务完成的代码/ codendles USB OUT transfersif( GPIFTRIG & 0 x80 ) / if GPIFerface IDLEif ( ! ( EP24FIFOS & 0 x02 ) ) / if theres a packethe peripheralfor EP2if ( EXTFIFONOTFULL

51、 ) / if the external FIFO is not fullif(enum_high_speed)SYNCDELAY;GPIFTCB1 = 0 x01; / setup tran SYNCDELAY;GPIFTCB0 = 0 x00;SYNCDELAY;ion count (512 bytes/2 for word wide - 0 x0100)elseSYNCDELAY;GPIFTCB1 = 0 x00; / setup tran SYNCDELAY;GPIFTCB0 = 0 x20;SYNCDELAY;ion count (64 bytes/2 for word wide -

52、 0 x20)Setup_FLOWSSYNCDELAY;E_Write(); / setup FLOWSE registers for FIFO Write operationGPIFTRIG = GPIF_EP2; / launch GPIF FIFO WRITE TranSYNCDELAY;ion from EP2 FIFOwhile( !( GPIFTRIG & 0 x80 ) ) / poll GPIFTRIG.7 GPIF Done bit; SYNCDELAY;Just like the single tranion firmware, if the in_enable flag

53、is not set, the code will just sit there andnot pros the INs.就像单个事务的固件，如果使能没有被设置，代码将会停在这里而不会执行 Ins。If the in_enable flag is set, the code will fall through and check if the GPIFerface is IDLE. It then goeson to check if the external FIFO is not empty. If the external FIFO has data, the code then det

54、ermines ifEP6 has room foreast one more data packet.如果使能端被设置了，将会失败，GOIF 逃到状态 IDLE.在将会去检查外部 FIFO 是否为空。如果 FIFO 有数据,则代码检测 EP6 是否有空间来装的数据包If EP6 has room foreast one more data packet, the TC value is setup for word wide operation (256).The appropriate TC value is setup for either high speed or full spee

55、d operation. The flow se registersare then setup for the FIFO Read tranion, and a write to the GPIFTRIG register with the appropriatebits triggers the tranion to fill the EP6 FIFO. The code then waits for the tranion to complete.Since EP6 is placedo auto mode, there is no need to explicitly write a

56、byte count value to indicate howmany bytes to send to the host. FX2 uses the EP6AUTOINLENH/L register values sehe DR_SetConfiguration() function for the auto commit size.enumeration time如果 EP6 有一个能放数量的空间，TC 的值将会设置成一个字宽。适当的 TC 值将能高速或全速运行。The flowse registers 被设置成 FIFO 读事务，写点数据到GPIFRIG 寄存器中，来填满 EP6 FI

57、FO 事务。等待完成事务的 Since EP6 is placedo auto mode不需要写一个字节的计数值来指示多少个字节被传送到主机。寄存器的值来在 DR_SetConfiguration()函数中 for the auto在列举的时候，FX2 使用 EP6AUTOINLENH/Lcommit size/ codendles USBransfersif (in_enable) / ifransfers are enabledif ( GPIFTRIG & 0 x80 ) / if GPIFerface IDLEif ( EXTFIFONOTEMPTY ) / if external F

58、IFO is not emptyif ( !( EP68FIFOS & 0 x01 ) ) / if EP6 FIFO is not fullif (enum_high_speed)SYNCDELAY;GPIFTCB1 = 0 x01; / setup tran SYNCDELAY;GPIFTCB0 = 0 x00; SYNCDELAY;elseSYNCDELAY;GPIFTCB1 = 0 x00; / setup tran SYNCDELAY;GPIFTCB0 = 0 x20; SYNCDELAY;ion count (512 bytes/2 for word wide - 0 x0100)

59、ion count (64 bytes/2 for word wide - 0 x20)Setup_FLOWSSYNCDELAY;E_Read(); / setup FLOWSE registers for FIFO Read operationGPIFTRIG = GPIFTRIGRD | GPIF_EP6; / launch GPIF FIFO READ Tranionto EP6FIFOSYNCDELAY;while ( !( GPIFTRIG & 0 x80 ) ) / poll GPIFTRIG.7 GPIF Done bit;SYNCDELAY;Running the exle f

60、PIF FIFO TranionsThe procedure for running the FIFO tranion exle is essentially the same as the Singletranion exle. Going through steps 1 through 3 of section 4.1.6 will allow the user to run theFIFO tranion exle as well. For running this verof the exle, unzip theFX2_to_extsyncFIFO GPIF FIFO Tranion