信号完整性分析_过孔、连接器、封装讲解课件

1、信号完整性分析Signal Integrity 第五讲：过孔、连接器、封装Vias, Connectors, and Packages第五讲: 过孔、连接器、封装Suggested Reading:1S Hall, G Hall, and J McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practice, Chapters 5 & 11 John Wiley & Sons, 2000.2H Johnson and M Graham, High-Speed Digit

2、al Design: A handbook of Black Magic, Chapters 7 & 9, Prentice Hall, 1993.3B Young, Digital Signal Integrity, Chapter 2, Prentice Hall, 2001.How are signal getting from one chip to another?Pentium 4 CPU goes here(socket)Memory ConnectorBridgechipVias, connectors, and packages are all important and n

3、ecessary parts of the path. Bridge chip packageTopics ViasDefinition: what are they and why do we need them?Electrical models of via parasiticsConnectorsDefinition: what are they and why do we need them?Electrical effectsInductanceSLEM-style approximationPower and ground pinsDesign considerations (t

4、radeoffs, rules of thumb)Topics (continued)PackagesDefinition: what they are and why we need them?Common types (e.g. flip-chip, bondwire) and history Creating package modelsEffect of a package on signal integrityDesign considerationsVertical connections between layers made by drilling a small hole a

5、nd filling it with conductive material.Connecting metal layers on silicon chips, within packages, and on printed circuit boards.capacitorchipchipPrinted Circuit BoardViasViasBarrel: conductive cylinder filling the drilled holePad: connects the barrel to the component/plane/traceAntipad: clearance ho

6、le between via and no-connect metal layerBarrelPadVia pad does not contact plane; void is the anti-padTrace connected to pad on layer 1.Via: Vertical Connection between LayersPadConnect metal planes of the same potential (e.g., all ground planes conductively attached)Carry a signal from a trace on o

7、ne layer to another (e.g., every data signal must get from the silicon bump down to the motherboard)Connect components (such as a capacitor) to a signal trace or a voltage plane.What Can a Via Do?PCB Via TypesBuried ViaThrough Hole ViaBlind ViaStacked ViaStep ViaPCB Via Types过孔(Via)过孔在多层PCB设计中非常重要，一

8、个过孔主要由三部分组成：孔；孔周围的焊盘区；POWER和GROUND层的隔离区。过孔的工艺过程过孔壁圆柱面上用化学沉积的方法镀上一层金属，用以连通中间各层需要连通的铜箔；过孔的上下两面做成普通的焊盘形状，可直接与上下两面的线路相通，也可不连；过孔可以起到电气连接、固定或定位器件的作用。PCB Via Types过孔一般又分为三类：盲孔、埋孔和通孔。盲孔(Blind Via),指位于印刷线路板的顶层和底层表面，具有一定深度，用于表层线路和下面的内层线路的连接，孔的深度与孔径通常不超过一定的比率。埋孔，(Buried Via),指位于印刷线路板内层的连接孔，它不会延伸到线路板的表面。 (盲孔与埋孔

9、两类孔都位于线路板的内层，层压前完成。)通孔 (Through Hole Via)，这种孔穿过整个线路板，可用于实现内部互连或作为元件的安装定位孔,大都是层压后完成。由于通孔在工艺上更易于实现，成本较低，所以一般印制电路板都使用通孔。SEM (Scanning Electronic Micrograph) Cross-Section Images Laser generated viaPhoto-defined viaPlasma generated viaCond. ink filled via激光打孔技术等离子干腐蚀技术More SEM Cross-section ImagesMicrov

10、iaPlated-through holeL_barrelC_padC_padVias are tiny structures unless Tvia delay 1/10 signal edgeThe via can be modeled as a lumped pi-model.To dark pink t-lineTo pink t-lineEquivalent Circuit Model of a ViaSame as low pass filter Cascading ElementsL_barrelC_padC_padL_barrelC_padTraceconnectionTrac

11、econnectionVia CapacitanceEffect is to slow the edgeEmpirical formula for pad capacitance:Via InductanceSeries L degrades signal integrityEmpirical formula for barrel inductance:D1: Via pad diameterD2: Via anti-pad diameterT: PCB thicknessh: via lengthd: barrel diameterVia Induced Delaycapacitive lo

12、ading + inductive loading + added distanceExample 1Model parasitics of viasLadder Model LCs are good to 1-2 GHzGNDPWRZ01Z01Z02Example 2200 MHz model parasitics of via stubGNDPWRLZ02Z01Z03via up to another signal layerSNG1SNG2Example 3Overall S-parameters can be obtained by the sub-networks using the

13、 ABCD or chain scattering matrixes.GNDPWRS02(f)Svia(f)S01(f)ConnectorsPentium III and Pentium II processor-based NLX motherboard supporting 66-MHz and 100-MHz System BusesVertically (new PCB perpendicular to mb)Horizontal (new PCB parallel to mb)Electrically/Mechanically connect one PCB board or PKG

14、 to another.Edge ConnectorsISAISA =Industry Standard Architecture Edge ConnectorsDIMMDIMM=Dual-Inline-Memory-ModulesEdge ConnectorsPCIPCI= Peripheral Component InterconnectEdge ConnectorsSLOT1APGPGA370PGA (Pin Grid Array) Sockets2D or 3D field solvers (HFSS) for better modelingSeries or mutual induc

15、tance have major effects1st order value can be estimated using empirical formulasSeries L slows edgeComplicated coupling introducing noiseShunt or mutual capacitanceSlows the system edge rateCapacitors sometimes added to reduce impedance discontinuity at connectorConnector crosstalkBecause of geomet

16、ry, mutual L has larger effect than mutual C. For first-order estimation, just consider L.Connector “Parasitic” ParametersConnector Effects r l r radius of round wire l length p perimeter of rectangular wireApproximation of mutual L between 2 connector pins sDIPPLCCQFPBGA CSP； 材料方面：金属、陶瓷陶瓷、塑料塑料； 引脚形

17、状：长引线直插短引线或无引线贴装球状凸点； 装配方式：通孔插装表面组装直接安装Package （封装）: Chip PackageConnections Made in a PackageAttachment of die to packageOn-package connectionsAttachment of package to PCBPackage Example: FCBGA Variations of PackagesAttachment of die to packageWirebondPeripheral I/O locationFlip chip,Area Array I/O

18、 locationAttachment of package to PCBPTH (Pin-Through-Hole), SMT (Surface Mount Technology)I/O locationsPeripheralArea ArrayPackage MaterialsPlastic,CeramicThin FilmAttachment of die to packageAttachment of die to packageA ring of bondwire attach pads on the periphery of the face of the die. On the

19、package, the bondwire lands on package routing. A bondwire is about 1mil（25.4um） in diameter, 50-500mils （1.27mm-12.7mm) long. A bondwire acts like an inductor.The die is placed face down. Solder balls attach the on-die pads to the surface of the package. The die pads are not limited to the peripher

20、y.The technology is self-aligning because the solder ball surface tension pulls the die pads into alignment with the package pads.Wire bondFlip-chipPros and Cons to Wire-Bond and Flip-ChipWire bondFlip-ChipInductanceMuch higher (1-5nH)Much less (.1nH)CrosstalkHigh Virtually none!CostCheap!HighMechan

21、icalGoodPhysical tolerances tightsince must align. ThermalBack of die attached to package for max surface area contact and max heat transfer out. Ugly: thermal coefficients of die and package must be similar otherwise expansion will break it. Cooling hard because die lifted off package by solder bal

22、ls.Die SizeLimits I/O since pads only around periphery.Die size can be minimized even many I/Os.Wirebond ModelingBall bondBond padChipRouting on PackagePackage dielectric layerPackage Substrate(reference plane in this case)A B C DTo approximate by hand:Subdivide the problem into sections for approxi

23、mationSections A and D are roughly perpendicular to the plane beneath, so they can be approximated using a simple straight-wire formula.For round wire, r2 driving chips?CPU 1CPU2ChipsetFull System Modeling Putting TogetherMulti-drop bus topologies are very common, for example a chipset with multiple

24、 processors.The effect of packaging on such bus topologies is dependent on the package stub length. Modeling of Small StubsZoZoZbTDstubSmall stub( ) treated as lumped C:ZoZoEffect of Shunt C on RisetimeStep Response:Equivalent risetime:U(t)Z0CZ0Z0Z0Note: (1) Vin=1/2 V (voltage division);(2): U(t)1/s

25、 in Laplace Transform domain. Modeling of Long Stubs More VariantsLong stub ( ) modeled as T-line; and Cload modeled as a segment of T-line ZoZoZbTDstubCloadZoZoZbTDstubTDcZbSimplification based on edge rateEffect of Package: Point to point bus topologyEffect of Package: Multi-drop bus topologySmall package stub effect:Long package stub effect:Effect of Package: Mul