PrimeTime时序分析流程和方法培训讲学

1、Good is good, but better carries it.精益求精，善益求善。PrimeTime时序分析流程和方法-PrimeTime时序分析流程和方法PrimeTime是Synopsys的一个单点的全芯片、门级静态时序分析器。它能分析大规模、同步、数字ASICS的时序。PrimeTime工作在设计的门级层次，并且和Synopsys其它工具整合得很紧密。,m8F0u)D;|$l(G!Z*n9基本特点和功能：DICDER,f5e&D6s3I(?时序检查方面：80n8y8H9z3g#P5u!?数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,V

2、CS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL建立和保持时序的检查（Setupandholdchecks）+h)b.P6v/Ak3!Z1B(Q数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,

3、DPLL重新覆盖和去除检查（Recoveryandremovalchecks）+i1z4I6O%YDigitalICDesignersforum时钟脉冲宽度检查(Clockpulsewidthchecks)DigitalICDesignersforum#F3H(Fy#z#m(e5.时钟门锁检查(Clock-gatingchecks)(8V$WJ$3O6E设计检查方面：%.VC6v;|*/VDICDER没有时钟端的寄存器&e9i98a$&k!j;E(a2F#i没有时序约束的结束点（endpoint）9E!j4V6K(T:v(q数字,集成电路,IC,FAQ,Designcompiler,数字信号处

4、理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL主从时钟分离（Master-slaveclockseparation）;l3Z-C8)z(D,n(_5c数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRA

5、M,SRAM,IIR,FIR,DPLL有多哥时钟的寄存器g)W2i+J7h,D(G.X*e对层次敏感的时钟（Level-sensitiveclocking）-xK$d:A.m(_+H.1DigitalICDesignersforum组合电路的反馈环（Combinationalfeedbackloops）DigitalICDesignersforum*6(I:o#F:x+|q设计规则检查，包括最大电容(maximumcapacitance)、最大传输时间(maximumtransition)和最大扇出(maximumfanout)*7-/W;K%_%K4Dp9e)2PrimeTime时序分析流程

6、和方法：05Q*i6X6qT在时序分析之前需要做的步骤：4N,D3n9J3?DigitalICDesignersforum1、建立设计环境3s6h;n#pV(LJf-nDigitalICDesignersforum-建立搜索路径（searchpath）和链接路径（linkpath）数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL7K/*N.a/

7、P%E:W!e-读入设计和库数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL$V+o&d,i.C#+T)o-链接顶层设计数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,

8、primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL3W7Cb4U-建立运作条件、连线负载模型、端口负载、驱动和传输时间a:Q!j8)k5.R0j/b2、说明时序声明（约束）DigitalICDesignersforum-#J;K.|3c*E9D5Y;L-定义时钟周期、波形、不确定性(uncertainty)和滞后时间(latency)DigitalICDesignersforum;Nq/(B!f3L9E#w-说明输入、输出端口的延时a/6Y-9a;k%s+S3、说明时序例外情况（timingexceptions）(j(D,B)zN-多周期路径（multicyclepa

9、ths）数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&!Q!z/J4&hC-不合法路径(falsepaths)(H6i(Vq;J;K-n2-说明最大和最小延时、路径分割（pathsegmentation）和失效弧（disabledarcs）/Kr.D(s(,c-j4、进行分析和生成报告$q%g.5m;F:u9D9h数字,集成电路,IC,FA

10、Q,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-检查时序数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL9t+Y56

11、T88vV*-生成约束报告数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL9e-m!_sd4R-生成路径时序报告数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,prim

12、etime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL*G%O2.x6D(j7l,H2#Cv!q8Z开始数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5Cx5h3t!z:H)T9Nq先建立目录并将PrimeTime本身所带的一个例子拷到新建的目录下，在下面的内容中将要用到这个例子。数字,集成电路,IC,FAQ,Designcom

13、piler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL4H8H0k+cSmkdirprimetime$q)s/3V?&LDICDERcdprimetime数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,

14、FIFO,SDRAM,SRAM,IIR,FIR,DPLL7P%ae,m7q.?xcpr$SYNOPSYS/doc/pt/tutorial.&?&B*H%X,a1bcdtutorial;.j%W%P;r61|,DigitalICDesignersforum确认目录中有以下这些文件：,O8TX/G!u!-AM2910.dbThedesign.dbforthetop-levelofthedesign9e-A-O$8d:g;G(BB&CONTROL.dbThedesign.dbfortheCONTROLblock#.nV4R-z4M)GDICDERREGCNT.dbThedesign.dbforthe

15、REGCNT0&4M1Ng&E0MUPC.dbThedesign.dbfortheUPCblock-D(U6A$F%S_:l8t6Z+MY.dataTheStampdatafilefortheYblock5qu+y-zK;数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLY.modTheStampmodelfilefortheYblock+s4C

16、3i,?7X6b-Q7v数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLY_lib.dbThelibrary.dbfortheY5o9b#C%_/b&tp3$r%rSTACK_lib.dbThelibrary.dbfortheSTACKblock数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,N

17、C,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL)E(y2t(Q+c5x7h.f*lpt_lib.dbThetechnologylibrary.dbDigitalICDesignersforum;?8U+&N+cx0_8Fstack.qtm.ptThequicktimingmodelscriptforthestackblock$U:F$o,g,S./o%L4r/p:m数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤

18、波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLoptimize.dcshThedc_shelloptimizationscriptDigitalICDesignersforum.C8w.J!F5_6x.Gtiming.dcshAnexampleDCshelltimingscriptfortranslationDigitalICDesignersforum6P*J2S7P1w6+3tutorial.ptThecompl

19、etePrimeTimetutorialscriptforyour数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL6G00)I7y:ureference.,z:b,G7L)H*B(rDICDER(Y2c,?0U4C数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,m

20、odelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL例子是一个AM2910微处理器，如图所示模块图。9|)c6Z#S(R1BC5PDigitalICDesignersforumattachment=141DICDER;D-0l6+h!x$E1h)T1m#M8t9F5VM8I运行PrimeTime：!u,V6tH8Q4i;|&数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix

21、,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shellDICDER9A,(b5D/m2C#Q:G5y7T0s)nDigitalICDesignersforum定义搜索路径和链接路径：N+x,q.U0o%H*,pt_shellsetsearch_path“.”数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,prim

22、etime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLk:|4u#z)V;r&X0pPt_shellsetlink_path“*pt_lib.dbSTACK_lib.dbY_lib.db”z.Z6n;:D1+D)T9P1%*pt_lib.dbSTACK_lib.dbY_lib.db:R&M+_*fi*Z/e数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,

23、IIR,FIR,DPLL;r7v?6N+.e5D;o-|8F4|$e读入设计：8m#t5p2Q.y080s6x:PrimeTime支持以下设计格式：!A,E%S%We#数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL.Synopsysdatabasefiles(.db)(Usetheread_dbcommand)&*N/X(F;Y%I.Veri

24、lognetlistfiles(Usetheread_verilogcommand)DigitalICDesignersforum-A&5t$D2B)m.ElectronicDesignInterchangeFormat(EDIF)netlistfiles(Usetheread_edifcommand.)7t-K+%r8D9k_H3I)M(M.VHDLnetlistfiles(Usetheread_vhdlcommand.)DigitalICDesignersforumW.s4Ku;g%j:S2_读入AM2910的顶层设计文件：数字,集成电路,IC,FAQ,Designcompiler,数字信

25、号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&%a6T7E;N:U,n%jpt_shellread_dbAM2910.dbr4o$?.g5F/p#V:Loadingdbfile/u/joe/primetime/tutorial/AM2910.db数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,

26、verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL1-a7b2V3w8x17_*3TN(?.f!数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLDigitalICDesignersforum4m;a+J1I*?:p链接设计：$Q3a8h!.j;j)J!?p

27、t_shelllink_designAM29107DB:,U71E-e数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLLoadingdbfile/u/joe/primetime/tutorial/pt_lib.db数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,m

28、odelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5|3_!z:qP9GlLoadingdbfile/u/joe/primetime/tutorial/STACK_lib.dbM*l2j3E4Uk%t1?.bLoadingdbfile/u/joe/primetime/tutorial/Y_lib.dbDICDER7+dB6n:GY1cLinkingdesignAM2010.1i3Q)w%F!m.I8tLoadingdbfile/u/joe/primetime/tutorial

29、/STACK.db数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLH!i$YL1E.数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDR

30、AM,SRAM,IIR,FIR,DPLL+L1E#R24M*Tr#MDesignsusedtolinkAM2910:#f%$N2_6/F/CONTROL,REGCNT,STACK,UPC,Y;_!K$C:u5V)gLibrariesusedtolinkAM2910:5s;t6#l.cDigitalICDesignersforumSTACK_lib,Y_lib,pt_lib45i/_!8R:3s95i*r数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL

31、,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLDesignAM2910wassuccessfullylinkedL3_8S3e3x9k9p+6eT;X)?60M4o2S,V%Q/E%v;JM2J+_h+Q-Pp$Q%b9数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL显示当前已载入的

32、设计：数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL.l4IO4|0u(6E.v3?pt_shelllist_designs6w)|$e.X2E/c;_5jZ数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,

33、VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL得到当前载入单元的信息：1R-a$n$1G8XR9v6w1Cpt_shellreport_cell)c)j/ON2d&C&y数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL/G:r+H,d;d&g编译一个标记模型（StampMod

34、el）：);Z*K0B+G7m8J数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL标记模型是一个诸如像DSP或RAMS那样复杂模块的静态时序模型。1x(L(h3o+(g/+n#o数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,ver

35、ilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL标记模型与.lib模型共存，而不能代替它们。(W2f,P(j0.N,N)x-建立标记模型是用在晶体管层次的设计上，在这个层次上没有门级网表。3n*r2F%*i1z0W2j:x数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR

36、,DPLL-标记模型语言是一种源代码语言，被编译成Synopsys的.db文件格式，可以被PrimeTime或DesignCompiler使用。数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL;A-?9W-XJ.w2X-P-标记模型包含引脚到引脚的时序弧、建立和保持时间数据、模式信息、引脚的电容和驱动能力等等。标记模型还能保存属性（面积等等）。

37、$r-D-y2H/qe6d1D2gB数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-三态输出、锁存器和内部生成的时钟都可以被建模。DigitalICDesignersforum,e56d-z&Q1+:E一个标记模型包括两种源代码文件格式：%U(g,E8K3.d数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,D

38、SP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-.mod文件&U5z(A0eL*v数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL仅包含引脚到引脚的弧的描述（没有延时数据）。

39、$D5y$i*r2C.6-.data文件4U1d4G,M7,R#NqDigitalICDesignersforum包含.mod文件中每条弧的延时数据。DICDER9f!-Wc-sw标记模型可以有多个.data文件来描述不同运作条件下的时序。DigitalICDesignersforum(_)!c/o66mo!lV两种文件格式都需要编译成一个.db模型。:G!5I;(y9D0T#&F7q#nh0数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,S

40、TA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL编译AM2910中Y模块的标记模型（标记源代码文件是Y.mod和Y.data）：#Xo8Lr,S:l数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shellcompile_stamp_model-model_fileY.mod;FR+Q&m

41、)r数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-data_fileY.data-outputY数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,

42、FIFO,SDRAM,SRAM,IIR,FIR,DPLL;7R3m0#U0r.t)7MWrotemodellibrarycoreto./Y_lib.dbh,y)y8T(c,H:B8_DICDERWrotemodelto./Y.db数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL/R5-YO)%J&W2QPrimeTime生成两个.db文件：数字

43、,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL2X1b4n;Y$R+t*o*w)v)N;J%yY_lib.db：一个库文件，包含一个单元(cell)。这个单元叫做核(core)。7m(l/D#R9e!vY.db：一个设计文件，引用Y_lib.db中的单元核。9v64E$i-s.H数字,集成电路,IC,FAQ,Designcompiler,数字信号

44、处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL3U6H7B%Z,H(XDigitalICDesignersforum3hb2D&x5a+818b6c编译一个快速时序模型(QuickTimingModel)：数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,ST

45、A,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLH5r&F&g$Z-Z4e可以为设计中还没有完成的模块建立一个快速时序模型，以使得完整的时序分析能够进行。通常的情形是：7f&S%W2R*数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-模块的HDL代码还没有完成时数字,集成电路,IC,FAQ,De

46、signcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5jl9z*J)V2s-为了划分设计，在评估阶段为实际设计进行时序预测、约束估计时,z#V93Q5Z(?#7-模块的标记模型还没有完成时数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,

47、IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL8j!N%S$(F1k一个快速时序模型是一组PrimeTime命令，而不是一种语言。为了方便和文档化可以将它们写在一个脚本文件中，然后保存为.db的格式。在PrimeTime和DesignCompile中快速时序模型很有用处。&z,t3h$v)L+?)H数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primeti

48、me,FIFO,SDRAM,SRAM,IIR,FIR,DPLL还可以将快速时序模型保存为标记模型，这是开始一个复杂标记模型的一种便利的方法。DICDER&l)l:(r:S&e/r$A3G例子中STACK模块的快速时序模型脚本文件是stack.qtm.pt，建立这个模型：数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL0L1O6S*p#P1R0h

49、:_/Ppt_shellsource-echostack.qtm.pt$O.X*|$L1J+|3A&.(y:aR(i)FX9r9p8O5pt_shellreport_qtm_model;|.l0N*H+k0|9(w,DigitalICDesignersforum.DigitalICDesignersforum0g0T!R5e9gpt_shellsave_qtm_model-outputSTACK-formatdb+c&I(t;MF;RG8I;y:nWrotemodellibrarycoreto./STACK_lib.db8t!F2BI.aC%tDICDERWrotemodelto./STACK

50、.db2!O8m+y2E/O8H#A*P,S97J9rj$i8ci&O)g9J:c)a;Y,q1G1AC#r数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL进行时序分析DICDER%gj5u4D?&d5b.f(B5配置运作环境/i9?v6*%aE*t数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS

51、,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL!x5n*l$H9N;P4L读入并链接AM2910设计：8rM,l5Y3M7数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shell

52、setsearch_path.+d1w58I,n:?*b4n数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shellsetlink_path*pt_lib.dbSTACK_lib.dbY_lib.db1u%Q9C9i2|1a(J2qpt_shellread_dbAM2910.db6F2.C9_8v3d)数字,集成电路,IC,FAQ,De

53、signcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shelllink_designAM2910(|;A9e*&e%&B:F,w数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FI

54、FO,SDRAM,SRAM,IIR,FIR,DPLL链接了AM2910会导致其它已经链接的设计变为不链接的状态。在内存里只允许有一个链接的设计。当一个设计不链接，所有时序信息将被去除，并会出现警告，这和DesignCompiler不同。如果需要保存所标注的信息，可以在链接一个新的设计之前用write_script命令。如果以后重新链接这个设计，只要运行这个脚本就可以了。数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,p

55、rimetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL#s-r5t1M!%O$x:X9z7T%U*c0t建立运作条件和连线负载模型：56V;X2e0p7I4D2w&_+Jk数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLPrimeTime在生成建立时序报告(setuptimingreports)时使用最大(Maximum)运

56、作条件和连线负载模型；在生成保持时序报告(holdtimingreports)时使用最小(Minimum)运作条件和连线负载模型。DigitalICDesignersforum8w4I(o-Mpt_shellset_operating_conditions-librarypt_lib-minBCCOM-maxWCCOMDICDER0s:x8KM9O3T1O%wpt_shellset_wire_load_81n-s$hQm9|-Qpt_shellset_wire_load_model-librarypt_lib-name05x05-min2?6an+|4l2H25pt_shellset_wire

57、_load_model-librarypt_lib-name20 x20max数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL8P3dB/i;#*-p如果运作条件在两个不同的库中，用set_min_library命令来在最大库和最小库中建立联系。:p?2I&o6k8N6&A:G得到一张库的列表：数字,集成电路,IC,FAQ,Designcomp

58、iler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&S9B*m8E0Xnpt_shelllist_librariesDICDER:w/s%:A:%i0I2Z9JLibraryRegistry:DigitalICDesignersforum3N8w;o9Y7MS7STACK_lib/home/gray/primetime/tutorial/0ic(x8H&s1SSTACK_lib.db:STACK

59、_lib&*i*8D;w%w#Y_lib/home/gray/primetime/tutorial/Y_lib.db:Y_lib2N;5D!J-a4BDICDER*pt_lib/home/gray/primetime/tutorial/6v/V*v4l1t.G26iDigitalICDesignersforumpt_lib.db:pt_lib数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,

60、SDRAM,SRAM,IIR,FIR,DPLL(F2r/_+F*F8z得到一个库的详细信息：6U!|5y9T$Apt_shellreport_libpt_lib8q,i15%k+g&)rDICDER4J3uc3m56x0Pu4_数字,集成电路,IC,FAQ,Designcompiler,数字信号处理,滤波器,DSP,VCS,NC,coverage,覆盖率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,验证,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL基本声明：数字,集成电路,IC,FAQ,Designcompiler,