数字逻辑设计及应用教学课件：6-3 编码器 三态门

1、 Class exerciserealize the logic function F with 3-to-8 decoder and logic gates.F = (X,Y,Z) ( 1, 2, 4, 5 ) Answer Key 1realize the logic function F with 3-to-8 decoder and logic gates.当使能端有效时Yi = MiF = (X,Y,Z) ( 1, 2, 4, 5 )ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VF Answer Key 2 realize the logic func

2、tion F with 3-to-8 decoder and logic gates.ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138ZYXF+5VF = (X,Y,Z) (0,3,6,7)当使能端有效时Yi = miExample 1Answer key for example 1Review of Last Class Decoder74X13874X139Cascading Binary DecodersBCD DecoderSeven-Segment DecodersG1G2A-LG2B-LBCAY0_LY1_LY7_LY2_LY3_LY4_LY5_LY6_L低位高位

3、Yi = EN miYi_L = Yi = ( EN mi )The 74x138 3-to-8 Decoder 74x139 The 74x139 Dual 2-to-4 DecoderN0N1N2N3EN_L+5VD0_LD7_LD8_LD15_L思路： 16个输出需要 2片74x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2任何时刻只有一片在工作。 4个输入中，N3位控制片选N2N1N0位控制输入design the 4-to-16 decoder二-十进制译码器0 0 0 0 0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1

4、 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10 1 1 1 1 1 1 1 1 11 0 1 1 1 1 1 1 1 11 1 0 1 1 1 1 1 1 11 1 1 0 1 1 1 1 1 11 1 1 1 0 1 1 1 1 11 1 1 1 1 0 1 1 1 11 1 1 1 1 1 0 1 1 11 1 1 1 1 1 1 0 1 11 1 1 1 1 1 1 1 0 11 1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1

5、 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1I3 I2 I1 I00123456789Y0_L Y9_L伪码任 意 项BCD DecoderSeven-Segment Decodersabcdefgdp公共阴极abcdefgd pNormally use (常用的有)：Light-Emitting Diodes（LED,半导体数码管）Liquid-Crystal Display（LCD,液晶数码管）abcdefgdp公共阳极七段显示译码器的真值表0 0 0 0 0 0 0 10 0 1 00 0 1

6、10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 11 1 1 1 1 1 00 1 1 0 0 0 01 1 0 1 1 0 11 1 1 1 0 0 10 1 1 0 0 1 11 0 1 1 0 1 10 0 1 1 1 1 11 1 1 0 0 0 01 1 1 1 1 1 11 1 1 0 0 1 10 0 0 1 1 0 10 0 1 1 0 0 10 1 0 0 0 1 11 0 0 1 0 1 10 0 0 1 1 1 10 0 0 0 0 0 0A3 A2 A

7、1 A0a b c d e f g01234567891011121314156.5 Encoder ENCODER (P408)If the devices output code has fewer bits than the input code, the device is usually called an encoder. Probably the simplest encoder to build is a 2n-to-n or binary encoder. encoder（编码器）Binary encoder Y0Y1Y2I0I1I71 0 0 0 0 0 0 0 0 0 0

8、0 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7Y2 Y1 Y0The truth table for a 8-to-3 binary decoder2ninputsnoutputsencoder （编码器）Y0 = I1 + I3 + I5 + I7Y1 = I2 + I3 + I6 + I7Y2 = I

9、4 + I5 + I6 + I7前提：任何时刻只有 一个输入端有效。1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7Y2 Y1 Y0The truth table for a 8-to-3 binary decoderBinary encoder Y0Y1Y2I0I

10、1I72ninputsnoutputsencoder （编码器）Y0 = I1 + I3 + I5 + I7Y1 = I2 + I3 + I6 + I7Y2 = I4 + I5 + I6 + I7前提：任何时刻只有 一个输入端有效。Trouble:When more than One Inputs are asserted?优先级（priority）1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0

11、 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7Y2 Y1 Y0The truth table for a 8-to-3 binary decoderIf multiple requests can be made simultaneously , how can the encoding device decide which? The solution is to assign priority to the input lines, so that when multiple requests are

12、asserted, the encoding device produces the number of the highest-priority requestor. Such a device is called a priority encoder. (P408)6.5.1 Priority Encoders (P410 ) (优先编码器)A2A1A0IDLEI7I6I5I4I3I2I1I0将 I0I7 转换为 H0H7，保证其中，任何时刻只有一个有效H7 = I7H6 = I6 I7H5 = I5 I6 I7H0 = I0 I1 I2 I6 I7A2 = H4 + H5 + H6 +

13、H7A1 = H2 + H3 + H6 + H7A0 = H1 + H3 + H5 + H7Highest-Priority数大优先 如果没有输入有效，则 IDLE 为1 IDLE = I1 I2 I6 I7Logic symbol for a generic 8-input priority encoder. 6.5.2 The 74x148 Priority Encoder (P411)The 74x148 is a commercially available, MSI 8-input priority encoder. EI-LI7-LI6-LI5-LI4-LI3-LI2-LI1-LI

14、0-LA2-LA1-LA0-LGS-LEO-Lits inputs and outputs are active low. inputsoutputsEnable output使能输出，用于级联EOGroup Select(选通输出)GSEI_L有效没有输入请求EO_L有效Enable Inputs使能输入EI-LEI_L有效有输入请求GS_L有效P411The EO_L signal is an enable output designed to be connected tothe EI_L input of another 148 that handles lower-priority

15、requests. (P412)lower-priority 148Higher-priority 148Two 74x148 cascaded to handle 16 requests.Q15_LQ8_LQ7_LQ0_LY3Y2Y1Y0GSQ15-L.QO-LY3Y2Y1Y00 XX.X11111.00000A2A1A0GSEOEII7I0A2A1A0GSEOEII7I0Q15_LQ8_LQ7_LQ0_LY0Y1Y2Y3GSTwo 74x148 cascaded to handle 16 requests.级联为164优先编码器输入：由864，需8片74x148每片优先级不同（怎样实现？）

16、 保证高位无输入请求时，次高位才工作 高位芯片的EO-L端接次高位芯片的EI-L端用8-3优先编码器74x148级联为64-6优先编码器A2A1A0GSEOEII7I0片间优先级的编码 利用第9片74x148 每片的GS端接到第9片的输入端 第9片的输出作为高3位（RA5RA3）片内优先级片间优先级 输出：6位低3位高3位8片输出A2A0通过或门作为最终输出的低3位RA2RA0(P413)分析判定优先级电路：（利用74x148 ） 8个_电平有效输入I0_LI7_L，_的优先级最高 地址输出A2A0，_电平有效 若输出AVALID高电平有效，则表示_A2A1A0GSEOEI74x148I7I0

17、I0_LI7_LA2A1A0AVALID低I0_L至少有一个输入有效高设计判定优先级电路：（利用74x148 ） 8个输入I0I7高电平有效，I7优先级最高 地址输出A2A0，高电平有效 如果没有输入有效， A2A0为000且输出IDLE=1有效I7I0A2A1A0IDLEA2A1A0GSEOEII7I074x1486.6 Three-State Devices (三态缓冲器)6.6 Three-State Devices (三态缓冲器) (P418)The most basic three-state device is a three-state buffer, often called

18、a three-state driver. The extra signal at the top of the symbol is a three-state enable input, which may be active high or active low ,When the enable input is asserted, the device behaves like an ordinary buffer or inverter. When the enable input is negated, the device output “floats”; that is, it

19、goes to a highimpedance (Hi-Z), disconnected state and functionally behaves as if it werent even there.6.6 Three-State Devices (三态缓冲器) (P418)三态缓冲器（三态驱动器）74x125：低电平使能，输出不反相74x126：高电平使能，输出不反相独立使能74x541：两个公共使能端，低电平使能， 施密特触发输入，输出不反相（P272图5-57） 标准SSI和MSI三态缓冲器Typical three-state devices are designed so th

20、at they go into the Hi-Z state faster than they come out of the Hi-Z state. 典型的三态器件，进入高阻态比离开高阻态快!EN1EN2_LEN3_LSSRC0SSRC1SSRC2ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138P0P1P7SDATAABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2一般器件不允许信号共享单个“同线”（party line）PQWSDATAABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2冲突（fighting）利用使能端进行时序控制.三态器件