数字逻辑设计及应用教学课件：3-2CMOS电路的电气特性

1、REVIEW OF LAST CLASS 1VDD = +5.0VVOUTVINTpTnVCCAZCMOS inverter常闭常开常闭常开inP 沟道N沟道2VCCAZVDD = +5.0VZABQ4Q1Q3CMOS 2-input NAND gateQ2CMOS inverter3 PMOS: when G is 0, Switch on; when G is 1, Switch off;NMOS: when G is 1, Switch on; when G is 0, Switch off;Two types of MOS transistor4CMOS inverter (INV)F

2、: get 1 from PMOS, get 0 from NMOS; When X=1, NMOS is on; When X=0, PMOS is on;5 NAND / NORNAND: NMOS serial , PMOS parallel; NOR: NMOS parallel, PMOS serial; 6 NAND / NORNAND: NMOS serial ; NOR: NMOS parallel;7 Output with positive logicBuffer AND8AND-OR-INVERT (COMS AOI )gate9 AOI / OAI103.4 Elect

3、rical Behavior of CMOS Circuits (CMOS电路的电气特性)Logic voltage levels. ( 逻辑电压电平)DC noise margins(直流噪声容限)Fanout.(扇出)Speed, Power consumption(速度、功耗)Noise, Electrostatic discharge(噪声、静电放电)Open-drain outputs. Three-state outputs (漏极开路输出、三态输出)113.5.1 Logic Levels and Noise Margins 逻辑电平和噪声容限VDD = +5.0VVOUTVIN

4、TpTn0 1 0112电压传输特性VDD = +5.0VVOUTVINTpTn0 1 01电流传输特性iDvI12VDD13CMOS逻辑系列（HC）电平规格高态不正常状态低态VOLmaxVILmaxVIHminVOHminVCC0.1V地0.1V0.7VCC0.3VCC典型值：VCC=5V+10%, Figure 3-26 Logic levels andnoise margins for the HC-series CMOS logic family. vcc014直流噪声容限（DC noise margin）多大的噪声会使最坏输出电压被破坏得不可被输入端识别.高态不正常状态低态VOLma

5、x=0.1VVILmax=1.35VVIHmin=3.15VVOHmin=4.4V30%VCC the LOW-state DC noise margin is 1.25 V =1.35-0.1(V)The HIGH state DC noise margin. Is 1.25 V=4.4-3.15(V) .1516VIK:输入钳位电压在输入端和输出端加钳位电路，使输入和输出不超过不超过规定电压。 173.5.2 Circuit Behavior with Resistive Loads (带电阻性负载的电路特性)(P103)183.5.2 Circuit Behavior with Resi

6、stive Loads(带电阻性负载的电路特性)(P103)要求有一定的驱动电流才能工作VCCAZVCCRThevRpRnVThev +VOUTVINaThvenin equivalent network19REMEMBERING THVENIN Any two-terminal circuit consisting of only voltage sources and resistors can be modeled by a Thvenin equivalent consisting of a single voltage source in series with a single r

7、esistor. The Thvenin voltage is the open-circuit voltage of the original circuit, and the Thvenin resistance is the Thvenin voltage divided by the short-circuit current of the original circuit.20Example 1 (P104)21Resistive model for CMOS LOW outputwith resistive load.22Resistive model for CMOS HIGH

8、outputwith resistive load.23VOLmaxIOLmax输出为低态时 VOUT 1MRn电阻性负载100 Sinking current吸收电流24VOHminIOHmax输出为高态时 VOUT = VOHmin输出端提供电流 sourcing current能提供的最大电流 IOHmax （拉电流）VCC = + 5.0VRpRn1M电阻性负载200 Sourcing current 提供电流25VOUT = 0VCC = + 5.0VRThevVThev +VIN = 1VCC = + 5.0VRThevVThev +VOUT = 1VIN = 0输出为低态时，估计

9、吸收电流：输出为高态时，估计提供电流：26EXAMPLE 2 (P107)273.5.3 Circuit Behavior with Nonideal Inputs (P108)283.5.3 Circuit Behavior with Nonideal Inputs非理想输入时的电路特性VCC = + 5.0V4002.5kVIN 1.5VVOUT 4.31VVCC = + 5.0V4k200VIN 3.5VVOUT 0.24V输出电压变坏（有电阻性负载时更差）更糟糕的是：Iwasted ， Pwasted 29Example 3 (P110)303.5.4 Fanout(P111)313.

10、5.4 Fanout （扇出）The fanout of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. The fanout depends not only on the characteristics of the output, but also on the inputs that it is driving. Fanout must be examined for both possible ou

11、tput states, HIGH and LOW. 在不超出其最坏情况负载规格的条件下， 一个逻辑门能驱动的输入端个数。扇出需考虑输出高电平和低电平两种状态 总扇出min（高态扇出，低态扇出）直流扇出 和 交流扇出32EXAMPLE 3 (P111) IImax for an HC-series CMOS input in any state is 1 A .The LOW-state fanout for an HC-series output driving HC-series inputs is 20. IImax for an HC-series CMOS input in any

12、state is 1 A .The HIGH-state fanout for an HC-series output driving HC-series inputs is 20.33EXAMPLE 4CMOS(TTLoutput level)CMOSCMOS the fanout of an HC-series output driving HC-series inputs at TTLlevels is 4000.直流扇出343.5.5 Effects of Loading(负载效应) 输出负载大于它的扇出能力时（P111） In the LOW state, the output vo

13、ltage (VOL) may increase beyond VOLmax.In the HIGH state, the output voltage (VOH) may fall below VOHmin.输出电压变差Propagation delay to the output may increase beyond specifications. Output rise and fall times may increase beyond their specifications.传输延迟和转换时间变长 The operating temperature of the device m

14、ay increase, thereby reducing the reliability of the device and eventually causing device failure. 温度可能升高，可靠性降低，器件失效.353.5.6 Unused Inputs(不用的CMOS输入端)不用的CMOS输入端绝对不能悬空XZ1k+5VXZ增加了驱动信号的电容负载，使操作变慢XZ1k363.6 CMOS Dynamic Electrical Behavior(P114)373.6 CMOS Dynamic Electrical Behavior CMOS动态电气特性考虑两个方面：速度功

15、耗转换时间（transition time）传播延迟（propagation delay）静态功耗（static power dissipation）动态功耗（dynamic power dissipation）383.6 CMOS Dynamic Electrical Behavior (CMOS动态电气特性) CMOS器件的速度和功耗在很大程度上取决于器件及其负载的动态特性。速度取决于两个特性：transition time（转换时间）propagation delay（传播延迟）逻辑电路的输出从一种状态变为另一种状态所需的时间从输入信号变化到产生输出信号变化所需的时间393.6.1 Tr

16、ansition Time (转换时间) rise time(上升时间) tr fall time(下降时间) tf the “on” transistor resistance(晶体管的“导通”电阻)stray capacitance(寄生电容)VCC = + 5.0VRLRpRnVL+CL电容两端电压不能突变在实际电路中可用时间常数近似转换时间P115 Figure 3-3640Example 4 (P117)estimates of 10 ns for fall time .41EXAMPLE 5 (P117)estimates of 20 ns for rise time .423.6.2 Propagation Delay(传播延迟)P83 图3-42VINVOUT信号通路：一个特定输入信号到逻辑元件的 特定输出信号所经历的电气通路。433.6.2 Propagation Delay(传播延迟)信号通路：一个特定输入信号到逻辑元件的 特定输出信号所经历的电气通路。443.6.3 Power Consumption(功率损耗)static power dissi