第十二章后端设计

1、第十二章第十二章后端设计后端设计OutlinesBackend Design FlowFloorplanPlace & RoutePhysical VerificationSignal IntegrityDFM/DFYSteps of Backend/Physical DesignSynthesis Floor Planning PlacementScan chain insertion and re-ordering ( optional )Clock Tree SynthesisRoutingParasitic and netlist extractionPower analysi

2、sSignal integrity checkingFinal timing analysis (STA and simulation)ECO (optional)LVS/DRCExport GDSII LVS/DRC using sign-off toolsBackend Flow with ECO Engineering Change Order (ECO)Achieved by adding small amount of cells in limited area, sizing buffers and routing the connectionsPrevent disturbing

3、 the placement and routing of the rest of the chipKeep in mind: Performance, Power, Size, ReliabilityIt is not impossible to develop “plug & Play” toolsFloorplanningBased on netlist, create areas of functionality on your chipDetermine the placement of blocksDetermine the placement of I/O pinsDet

4、ermine the power supply strategy Give feedback on how easy your floorplan might be to wire (Global routing) and how big the chip isChip Floorplanning ConsiderationsChip level floorplanningnHigh speed block issue nLocation affect the timing performancenAnalog block issue nclean Vdd/Vss; minimal spaci

5、ng to digital block; IO locationnDie size issuenPin limited; Core limitednPower-Ground routing issuenPower ring width according to power analysisnPower strip/mesh spacingnPin placement and IO ring issue (will be talked in next class)nPad pitch vs. bounding rule; ESD; noise isolation; Die Size Issue

6、cont.Determine the area for standard cells “Utilization” 70% ? 80%? 90%?nExtra space for clk tree synthesisnExtra space for scan chainnLayers for routingHard Macro PlacementMacros are generally placed around the peripheral I/O ring nA contiguous area for standard cells.nHigher freedom for your place

7、-and-route tools during placement and routing of the standard cellsThe goal of macro placement is to:nReduce timing-critical paths between the macros and interfacing logic.nReduce interconnections in the following order:n Chip I/O to macrosn Macro to macro n Macro to standard cell blocksPower/Ground

8、 DevelopmentIR Drop and ElectromigrationnPower-net IR drop degrades the supply voltage levelnExcessive current density in metal wire causes electromigration failure which breaks metal connectionnMore significant IR drop effect when Vdd gets smallernHigher current density when metal wire width is sma

9、llerVddRPower/Ground Development-cont.Ring structurenPower rings around all layout blocksnMajor power trunks between layout blocksnDifficult to guarantee the worst IR dropStrap structurenSimple, easy for routingMesh structurenEvenly distribute of IRnSpacing of Power strips consideration IR drop anal

10、ysisnFix the problem in early stage P/G StructuresBe Ware of Maximum Width RuleMaximum wire width limit due to thermal stress and local density rulesSlotting vs. “bus” of thin wiresDisadvantage of slotting:nSlots may not be aligned with current flownTrue IR drop not known until after slottingEspecia

11、l happen for Power/Ground ringsM1M1GNDGNDGNDGNDCommonly used for power/groundPlacement Based on a given floorplan, determine the location of cells in a given netlist Goals & objectives RoutabilityGuarantee the router can complete the routing step (Global routing) TimingMinimize all critical net

12、delays Minimize die sizeMake the chip as dense as possible Signal IntegrityCheck feasibility of routing after placementnLogic effort - for those paths with positive slack, reduce cell sizeCongestion and FixBeforeAfterCongestion areasRoutingComplete power/ground/clock routing (clock tree synthesis) C

13、omplete detailed wire routing, conform wiring rule and order)Improve the densityMinimize the layer changesImprove critical path and meet timing requirementProduce a routed design free of DRC/LVS violationsGeneral Routing Flow Clock Tree SynthesisnAdd buffers/inverters, minimize clk skew and delayPos

14、t Placement Optimization (PPO)nFix setup violationPre-Route Standard CellsnVDD/VSS rails on metal 1nVerify PG connection and routingRoute Group Net nclocksnbus routingPost-Route CTOnFix clk skew and insertion delayGlobal Routingncritical pathnlong wire, interconnectionRouting flow cont.Track Assignm

15、ent & Detail RoutingnWire connectionSearch & Repair (DRC/LVS)nfix routing violation (unconnected nets, shorts)Post Route OptimizationnFix timingCoarse LVS & DRC checkingnmetal width, notch & gap checkingData Outputnstream out: gds2 formatnverilog out: hierarchy (PT) / non-hierarchy (

16、for Hercules)nparasitic out: spef format (cell view)Clock Tree Synthesis Objective: nminimize clock skewnoptimize clock buffersBasic CTS Flow & Concepts Clock ConstraintDefine:nClk source: root pin, target insertion delay, target transition time at clk portnClk endpoint: Synchronous pin, ignore/

17、exclude pinnDriving cell, clk cell, delay cell: buffers, inverters, special clk cells nDRC: maximum transition delay, maximum net capacitance, maximum fanout, clk number of buffer levelsClock Skew Global Skew and Local SkewnGlobal skewnGlobal skew is the clock arrival time difference between any two

18、 flip-flops.nLocal skewnLocal skew is the clock arrival time difference between two flip-flops that are adjacent through combinational logic.Concept of Useful SkewUseful skew is a method of intentionally skewing a clock to improve the timing on a circuit.It is also commonly used in ECOWarning: Could

19、 cause problem in DFT scan insertion Use CTS for High-Fanout Net SynthesisHigh-fanout pins: rest, scan_enNeed to balance high-fanout pins to guarantee the functionalityUsing CTS tool: high-fanout nets by inserting a balanced buffer treenTo minimize both skew and insertion delaynBut should avoid usin

20、g large buffers for power savingLarge SoC Clock DistributionPartition the design to several blocksCTS for each blockClk tree network at top levelExternal clockIP Coreor ModuleCore InternalClock NetPLLGlobal Clock NetH Tree for Top Clock NetworkUse big buffer to balance delay and clk skewnEqual dista

21、nce, equal loads, equal driving ability Clock Distribution Case Study: Pentium SpinesFROM PLLKurd et al., A multigigahertz clocking scheme for the Pentium 4 microprocessor, JSSC2001Clock Distribution Case Study: Intels Itanium H Tree ClockingTam et al., Clock generation and distribution for the firs

22、t IA-64 microprocessor, JSSC 2000IssuesLarge amount of clock buffers added on clock treenPower consumptionnNoise to supply linesReduce power consumption nWide wire widthsnClock gating cell placementnLimitation of using large clock buffer cellsReduce noise nSpecial clock buffer cells with decoupling

23、capacitorExtractionWhen complete detailed routenWrite out the hierarchical netlist and parasitic for back annotationData management on huge file of extracted parasitic dataAccurate RC and timing model for nanometer designnWidth and spacing dependencenResistance shielding nLocal density effectSDF Bac

24、k AnnotationUsed in cell-based design flowPerforms delay calculation on parasitic RCs in interconnect wiresDSPF - Detailed Standard Parasitic FormatSPEF Standard Parasitic exchange FormatSDF - Standard Delay Format used for post-layout simulation nCan be convert from PrimeTimePhysical Verification D

25、RC - Design Rule checknVerify the manufacturing rules, example:nInternal layer checksnWide metal checksnMetal slotting needed for wide metalnLayer-to-layer checksnDFM/DFYnExample: Antenna Rule CheckLVS Layout vs. SchematicsnCompare layout to schematics- every cell and netDRC Trends and Challenge75%

26、time on metal layer and via checkERC-type checks increasingRise of pre-tapeout DFM utilitiesNumber of Design Rules by ProcessNumber of Design Rules by ProcessNodeNode020040060080035025018015013090(nm)(nm)LVSLayout vs. Schematic (LVS)nCheck physical layout against functional gate level schematic to e

27、nsure all intended connectivity has been maintainednSteps:nExtract the netlist from layout (GDSII)nCompare the netlist with the one after routing and optimization Hints: nMost of LVS errors are caused by manual layout or congestionn“Virtual connect” (connected by text) could cause a killer failureSi

28、gnal IntegritySignal Integrity is the ability of a signal to generate correct response in a circuitnSignal has digital levels at appropriate and required voltage levels at required instants of timeCrosstalk, IR Drop, ElectromigrationLayout Parasitic vs. Circuit PerformanceInterconnect parasitic resi

29、stors, capacitors and inductors cause extra timing delayAdditional power consumption caused by parasitic RC Inter-wire capacitances cause coupling noise and will dominate interconnect wire delaysParasitic resistances in power supply cause voltage drop and may degrade circuit performanceHigher curren

30、t density in power net may cause electromigration failureInductance EffectsInductive coupling effect is significant for long interconnects and for very fast signal edge rateInductive coupling is negligible at short trace interconnects, since the edge trace is long compared to the flight time of the

31、signalInductance extraction and simulation are more difficult than capacitanceCLCrosstalk AnalysisDefinitionnAggressor: generating crosstalknVictim: receiving crosstalkTiming sensitivenCrosstalk analysis consisting signal transition timing window can eliminate pessimistic delay calculationnThe cross

32、talk spike is related to capacitance value and the victim driver impedanceCrosstalk Analysis cont.Timing sensitiveCrosstalk PreventionPrevent crosstalk from synthesis stage nMinimize the driving size on those non-critical path to reduce the number of aggressors nApply max transition time (set_max_tr

33、ansition) in physical synthesis/placement to avoid long netsCrosstalk Prevention cont.From routing stagenEffective spacing between noise region and quite region nShielding between critical pathsCrosstalk Prevention cont.From routing stage cont.nBuffer insertionnInserted buffer breaks up the coupling

34、 capacitance of long wireCrosstalk Prevention cont.From routing stage cont.nBuffer sizingnIncrease the driver size of victimnDecrease the driver size of aggressornTrack reorderingnTrack reordering is based on timing windowCrosstalk Prevention cont.For inductance crosstalknCoplanar ShieldsnReference

35、PlannStagger Inverter/BufferElectromigration EffectsThe electrons flow through the wires and collide w/metal atoms, producing a force that causes the wires to breakCaused by the high current densities and high frequencies going through the long, very thin metal wiresMTTF (Mean Time To Failure) incre

36、ases when current density and temperature increaseCan be eliminated by using the appropriate wire sizing Open CircuitShort circuitFix EM Controlling current density to limit electromigration failure is needed in design and verificationLayout optimization:nIncrease the power line width, layernIncreas

37、e the power padsnIncrease the connection IssuesnMore metal (add 8% cost per layer)nLarger, slower designs (grow in x and y) Other ConsiderationsESD (will be talked in next class)Package vs. performance (will be talked in next class)DFM/DFYDFM/DFY90nm and below technologies challenges in yieldDFM Des

38、ign for ManufacturabilityDFY Design for Yield DFM and DFYDFM is the management of technology constraints (sizing rules) applied to the layoutA manufacturable design however is not necessarily a high-robust or high-yielding design.DFY, as part of Design for Manufacturability, concentrates on the deve

39、lopment and quality of the circuit design in the pre- and post-layout phase. DFY is the management of design sensitivities to the manufacturing process and helps to guarantee high-yielding devicesDFM/DFY MethodologyOptimal resolution enhancement technology (RET) nMask and exposure nOptical Proximity

40、 correction (OPC)nPhase Shaft Mask (PSM)Yield enhancement and optimization technologynDFM rules implementationnTo overcome limits of OPCnYield checking during the layout stagenSupported by EDA toolsWhy Need RET?Wavelength used vs process generationDesign for Manufacturing Not all the things can be d

41、one by mask and exposure:nCorrections are not completenSome designs cannot be built at all with certain RET technologiesnOf those that CAN be built, some are more manufacturable after RET than othersDFM/DFY-driven routingnOPC-driven routingnPSC-driven placementnDFM rule implementationDFM/Y RulesLimi

42、t the use of minimal poly-enclosed gates, minimally enclosed vias and singly contacted linesnBetter yieldnLess resistanceExample: Via Void rules - doubled vias Current DFM/Y Design Flow Supported Load DesignPerform antenna fixesAdd contacts/viaMetal Fill & SlottingVerify LVS and DRCWhy Need Doub

43、le Vias?Copper processing causes new problems for viasnVoids in Cu migrate under thermal stress towards viasnIf enough voids migrate to a via it can cause failurenWorse at 90/65nm due to increased stress of smaller viaVoids can migrate long distances 10 micronsVoids can migrate around cornersYield vs. AreaAntenna RulesAntenna rules have nothing to do with traditional definition of antennanReally a collector of static charge, not electromagnetic radiationAntenna problem only happens during manufacturingnPlasma-based pro