实验三十一交通灯实验

1、众友科技 数字逻辑电路实验三十一 交通灯实验一、实验目的 1、熟悉VHDL语言编程，了解实际设计中的优化方案。 2、熟悉在Max+plus和ispDesignEXPERT软件中使用硬件描述语言输入，编译的方法。 3、了解几种硬件描述语言的语言规范（VHDL，AHDL，Verilog HDL等）。二、实验硬件要求 1、数字逻辑电路实验箱。 2、数字逻辑电路实验箱实验箱上交通灯模块。 3、LATTICE 1032E适配板和ALTERA 7128适配板。三、实验内容 1、用硬件描述语言实现交通灯实验。 2、观察实验现象，并对比实际生活中的交通灯。四、实验原理要完成本实验，首先必须了解交通路灯的燃灭规

2、律。本实验需要用到实验箱上交通灯模块中的发光二极管，即红、黄、绿各三个。依人们的交通常规，“红灯停，绿灯行，黄灯提醒”。其交通灯的燃灭规律为：初始态是两个路口的红灯全亮，之后，东西路口的绿灯亮，南北路口的红灯亮，东西方向通车，延时一段时间后，东西路口绿灯灭，黄灯开始闪烁。闪烁若干次后，东西路口红灯亮，而同时南北路口的绿灯亮，南北方向开始通车，延时一段时间后，南北路口的绿灯灭，黄灯开始闪烁。闪烁若干次后，再切换到东西路口方向，重复上述过程。在实验中使用数码管显示时间。时间控制由TBJSA和DK两个模块联合控制。其中TBJSA为计数器，将脉冲信号从0到15循环计数。DK控制在不同时间段的发光二极管

3、的输出提示。五、实验步骤 1、硬件连接（两个显示时间用的数码管必须为同极性，或共阳或共阴）CPD：接1Hz左右的时钟信号。CPS：接10KHz左右的时钟信号。LR1-LR4：接交通灯模块的R1-R4。LG1-LG4：接交通灯模块的G1-G4。LY1-LY4：接交通灯模块的Y1-Y4。D0-D6：接数码管模块的A，B，C，D，E，F，G。SEL0：接实验箱数码管模块的右边的数码管SEL1：接实验箱数码管模块的左边的数码管。 2、软件下载 3、实验记录六、实验VHDL语言程序LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY t1 ISPORT(cpd,

4、cps : INSTD_LOGIC;lr,lg,ly : OUTSTD_LOGIC_VECTOR(4 downto 1);d : OUT STD_LOGIC_VECTOR(6 downto 0);sel : OUT STD_LOGIC_VECTOR(2 downto 0);END t1;ARCHITECTURE a OF t1 ISCOMPONENT tbjsaPORT(cp : INSTD_LOGIC;q : OUTSTD_LOGIC_VECTOR(4 downto 0);END COMPONENT;COMPONENT tbjsbPORT(cp : INSTD_LOGIC;q : OUTST

5、D_LOGIC_VECTOR(2 downto 0);END COMPONENT;COMPONENT dkPORT(cp : IN STD_LOGIC;sj : INSTD_LOGIC_VECTOR(4 downto 1);lr,lg,ly : OUTSTD_LOGIC_VECTOR(4 downto 1);END COMPONENT;COMPONENT sxPORT(sj : IN STD_LOGIC_VECTOR(3 downto 0);kz : IN STD_LOGIC;d : OUTSTD_LOGIC_VECTOR(6 downto 0);END COMPONENT;SIGNAL ns

6、j : STD_LOGIC_VECTOR(4 downto 0);SIGNAL nwk : STD_LOGIC_VECTOR(2 downto 0);BEGINl_a: tbjsa PORT MAP (cpd,nsj);l_b: tbjsb PORT MAP (cps,nwk);l_c: dk PORT MAP (cpd,nsj(4 downto 1),lr,lg,ly);l_d: sx PORT MAP (nsj(3 downto 0),nwk(0),d);sel <= nwk;END a;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY

7、sx ISPORT(sj : IN STD_LOGIC_VECTOR(3 downto 0);kz : IN STD_LOGIC;d : OUTSTD_LOGIC_VECTOR(6 downto 0);END sx;ARCHITECTURE a OF sx ISSIGNAL nsjh,nsjl : STD_LOGIC_VECTOR(6 downto 0);BEGINwith sj selectnsjh <= "0000110" when "1111", "0000110" when "1110", "

8、;0000110" when "1101", "0000110" when "1100", "0000110" when "1011", "0000110" when "1010", "0000000" when others;with sj selectnsjl <= "0111111" when "0000", "0000110" when "00

9、01", "1011011" when "0010", "1001111" when "0011", "1100110" when "0100", "1101101" when "0101", "1111101" when "0110", "0000111" when "0111", "1111111" when "1

10、000", "1101111" when "1001", "0111111" when "1010", "0000110" when "1011", "1011011" when "1100", "1001111" when "1101", "1100110" when "1110", "1101101" when "

11、1111", "0000000" when others;with kz selectd <= nsjl when '0', nsjh when '1', "0000000" when others;END a;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY tbjsa ISPORT(cp : INSTD_LOGIC;q : OUTSTD_LOGIC_VECTOR(4 downto 0);END tbjsa;ARCHITECTURE a OF tbjsa IS

12、COMPONENT JKFF PORT (j : IN STD_LOGIC; k : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC);END COMPONENT;SIGNAL vcc : STD_LOGIC;SIGNAL njk,nq : STD_LOGIC_VECTOR(4 downto 0);BEGINvcc <= '1'njk(0) <= '1'njk(1) <= nq(0);njk(2) <=

13、nq(0)and nq(1);njk(3) <= nq(0)and nq(1)and nq(2);njk(4) <= nq(0)and nq(1)and nq(2)and nq(3);l1:FOR i IN 4 downto 0 GENERATEn_jk: JKFF PORT MAP (njk(i),njk(i),cp,vcc,vcc,nq(i);q(i) <= not nq(i);END GENERATE;END a;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY tbjsb ISPORT(cp : INSTD_LOGIC;q

14、 : OUTSTD_LOGIC_VECTOR(2 downto 0);END tbjsb;ARCHITECTURE a OF tbjsb ISCOMPONENT JKFF PORT (j : IN STD_LOGIC; k : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC);END COMPONENT;SIGNAL vcc : STD_LOGIC;SIGNAL njk,nq : STD_LOGIC_VECTOR(1 downto 0);BEGINvcc &l

15、t;= '1'njk(0) <= '1'njk(1) <= nq(0);l1:FOR i IN 1 downto 0 GENERATEn_jk: JKFF PORT MAP (njk(i),njk(i),cp,vcc,vcc,nq(i);END GENERATE;q(0) <= nq(0);q(1) <= '0'q(2) <= nq(1);END a;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY dk ISPORT(cp : IN STD_LOGIC;sj : INS

16、TD_LOGIC_VECTOR(4 downto 1);lr,lg,ly : OUTSTD_LOGIC_VECTOR(4 downto 1);END dk;ARCHITECTURE a OF dk ISSIGNAL ra,rb,ga,gb,ya,yb : STD_LOGIC;BEGINra <= sj(4);rb <= not sj(4);ga <= (not sj(4)and(sj(3)or(sj(2)and sj(1)or(sj(2)xor sj(1)and cp);gb <= sj(4)and(sj(3)or(sj(2)and sj(1)or(sj(2)xor sj(1)and cp);ya <= (not sj(4)and(not(sj(3)or sj(2)or sj(1);yb <= sj(4)and(not(sj(3)or sj(2)or sj(1);lr(1) <= ra;lr(2) <= rb;lr(3)