cameralink_v2.0中文版

1、1 Camera link1.1引言Camera link是一个为视觉应用设计的通讯接口，它对 NS的Channel link 技术进行了拓展.1.2 约定文档中“ shall ”表示强制要求，“ can ”表示可选。1.3 LVDS技术描述低压差分信号是一个高速、低功耗、常用的接口标准。又称为 ANSI/TIS/EIA-644 。最大传输 速率1.923Gbps 。差分信号能承受土的蜘莫噪声。1.4 Channel Link国家半导体（NS）为了解决平板显示问题开发了channel link技术，基于LVDS物理层。channel link 包含一个发一个收，发送端接收28位的单端信号和一个

2、单端时钟，数据按照7:1串行化，这样需要 4根LVDS数据线和一个LVDS时钟线。接收端接收 4个LVDS数据流和一个专用时钟，并转换成28bits数据和一个时钟。示意图如下Fgure 1-1: Channsl Link OperathDn当|3小 Sowon.Ll> 1.6 BhpsData LVDS) 手，口口。口ata（LVDS）-本皿匚口ata （LV运）李皿Dta jLVDS) * iqq匚Cloak (LVDS)拿小口TTLgos1.5 Camera Link 的 5 种配置方式每种配置支持不同的位宽，方便制造商选择不同的配置来匹配他们的产品。?lite -Supports

3、up to 10 bits, one connector?base-Supports up to 24 bits, one connector?medium - Supports up to 48 bits, two connectors?full -Supports up to 64 bits, two connectors?80 bit -Supports up to 80 bits, two connectors1.6 技术优势1.6.1 较小的连接器和线缆28bits 可以通过 5 个 LVDS 对传输，降低了接插件的大小，为更小的相机提供了可能。1.6.2 高数据传输速率Channe

4、l Link 家族芯片的最大速率可达2.38Gbps ，符合当前传输速度不断提高的趋势2 相机信号要求2.1 介绍主要介绍信号的定义， Camera Link 线缆提供控制信号、串行通信和视频数据。2.2 视频数据图像数据和图像数据使能在channel link 总线上传输。2.2.1 Camera Link Base/Medium/FullCamera Link Base/Medium/Full 定义了 4 个使能信号，描述如下?FVAL 一场有效，高期间可以输出行有效，FVAL和第一个有效行前沿没有间隔?LVAL一行有效，高期间可以输出数据有效，LVAL和第一个像素有效没有间隔?DVAL一

5、数据有效，高有效 ?Spare 剩余，备用相机上的每个channellink 芯片都必须提供所有定义的使能信号， 相机需保证所有未用到的数据位必须嵌位到一个已知值。图像数据位分布请参考第四、五部分。2.2.2 Camera Link Lite?FVAL 一场有效，高期间可以输出行有效，FVAL和第一个有效行前沿没有间隔?LVAL一行有效，高期间可以输出数据有效，LVAL和第一个像素有效没有间隔?DVAL一数据有效，高有效?Spare 这种配置下没有分配相机上的每个channellink 芯片都必须提供上述 3 个使能信号， 相机需保证所有未用到的数据位必须嵌位到一个已知值。图像数据位分布请参考

6、第 4 、 5 章。2.2.3 Camera Link 80bit80bit 配置模式使用了一些使能信号来传输数据，所有的剩余用来传输数据。使能信号定义如下?FVAL 场有效，高期间可以输出行有效，只提供给第一片 channel link 芯片?LVAL 行有效，高期间可以输出数据有效，提供给所有channel link 芯片备注： DVAL 和 Spare 信号用来传输数据相机必须给基本channellink 芯片提供 FVAL 和 LVAL 信号，其他两片必须提供LVAL ，其他信号用作数据。2.3 相机控制信号2.3.1 Camera Link Base/Medium/Full保留 4

7、个 LVDS 信号对，用来做通用相机控制，对采集卡来说是输出，相机是输入，相机制造商可以根据他们的产品定义这些信号。?Camera Control 1 (CC1)?Camera Control 2 (CC2)?Camera Control 3 (CC3)?Camera Control 4 (CC4)2.3.2 Camera Link Lite保留 1 个 LVDS 信号对，用来做通用相机控制，对采集卡来说是输出，相机是输入，相机制造商可以根据他们的产品定义这个信号。?Camera Control (CC)2.3.3 Camera Link 80bit同 Camera Link Base/Med

8、ium/Full2.4 通讯2.4.1 Camera Link Base/Medium/Full2 个 LVDS 信号对，用来做相机和采集卡间的异步串行通讯，波特率至少 9600 。信号包含?SerTFG to 采集卡的差分对?SerTC to 相机的差分对串行接口有如下特性一个开始位，一个停止位，没有奇偶校验，没有握手。采集卡厂商必须提供一个API 来使用这个串行通讯接口，详细参见第 8 章2.4.2 Camera Link Lite1个LVDS信号对，用来做从采集卡向相机异步串行通讯，从相机到采集卡的通讯在数据的一个LVDS信号对上。?SerTCto相机的差分对?SerTFGto采集卡的差

9、分对，这个信号分配到数据个差分对上，详细参见bit分配，传输速率不是时钟速率，根据相机中的波特率来定。串行接口有如下特性一个开始位，一个停止位，没有奇偶校验，没有握手。采集卡厂商必须提供一个 API来使用这个串行通讯接口，详细参见第 8章2.4.3 Camera Link 80bit同 Camera Link Base/Medium/Full3端口分配不同配置的命名如下：? Lite/Base -1个Channel Link 芯片，1个线缆连接器?Medium -2个Channel Link芯片，2个线缆连接器? Full/80 bit -3个Channel Link芯片，2个线缆连接器3.1

10、 端口定义-所有配置一个端口定位一个 8位的字，LSB是bit0 , MSB是bit7,。 CameraLink 使用8个端口，从A-J ,下表中列出了各种配置的具体情况。ConfigurationPorts SupportedNumber of ChipsNumber of onnectorsLiteA, B (up to 10 bits only)11BaseA, B, C11MediumA, B, C, D, E, F22FullA, B, C, D, E, F, G, H3280 bitA, B, C, D, E, F, G, H, I, J323.2 相机硬件布局和框图3.2.1 B

11、ase/Medium/Full 配置Camera Hardware Routing PC MemoryPortHPort GPcrtFPortEPcrtC12 bit 心口 116bft：H0-H7 SS，LJB bit: G0-G7 S412 bit: D0-D7S38 b忙 F0¥712 bit；C8-C118 bit: E0-E7 12bit;C(bC7*8bfcDOD7 BYTE 8BYTE?BYTE 6BYTE 5Empos?0BYTE 4PurtC8t*COC7LJ 12 bit; B0-B7BYTE 3Pert E3 bit： BOB?12 bit Afr-A11Por

12、t A8 bit: Ad*7 12blt:AO-A7BYTE 2BYTEIFigure 1 Data Routing for Base, Medium, and Full ConfigurationsIW,=WURorTA-iCSIRS A ACY1Frame Qratta LMLiPwu1EMAUSPPORT Q.HZ30PertKR CSirTFQStrTGGkw«Cmbnal 1AMSTAB DJEFIAMUFVAU EWLSFARG8TWB1Figure 2 Block Diagram of Base, Medium, and Full Configuration3.2.2

13、Lite Configurations卜图列出了 80bit 10tap/8bit的配置和布局和80bit 8tap/10bit的配置和布局。10 bit At A9BTE2LiteBY1 E1Figure 3 Data Routing for Lite ConfigurationsPortFW. LVAl D'JALPoll 丸 BSoiTFCSTR.nA BCLKXCfroraConuol 理 qkucon-#D6L-=ocWJIL*FVAL LVALDVALPuri A, BStirTFCSTRB jLB_ Cflirtirvi ControlXDX2CLKXFigure 4 B

14、lock Diagram of Lite Configuration3.2.3 80 bit Configurations1。相ps 杷-HitFor JPon lPml HPon gBYTE 10BYTESHTTE7BYTE BJO* J710 -IFHO - H7go-a?J MFF0 - FTPod DPonCPbrt BPort AED - E70-1 1 E. OBYTEBYTESBYTtSBYTE 1D0-D7CO© BO - B7AO-A7Part JBVTE 10E0 E FO, Fl, GO Gt HO. HlPort 1BVTE QAC A1, BO, B1CO

15、Cl, DO, DiPurl HBrT= 6H2-H9Port GBVTE 7G2Q9I Pori FBYTE GF2F92 Por： EBF 5E2-E9Pud CO2-D9Pori CBYTE 3C2-C9 APtrn日BVTE 2-B2-B9Ron ABKTE 1AZ-A9Figure 5 Data Routing for 80 bit ConfigurationsFrameGrabberLVAL PoriSTRBLVALPortD,E,F tt-14STR日SifTCFV*L LVALPori A.a C, 叫HSTUBCamsriConlroi i,2, 3 4Figure 6 Bl

16、ock Diagram of 80 bit, 10-tap/8-bit ConfigurationLVALSTRR>E 1STR日Figure 7 Block Diagram of 80 bit, 8-tap/10-bit ConfigurationCameraPan G5 - G7,FVAL, LVAL Pori A, a. C, M mSTRBCamera Control三.J*-Z1kn>_23LKZt一：任叽空XI>xaKAOJQCS*TFG氏mNSTRBLVALPartD2-GO-茸TRBIrtoxBLVALPert 4 B, J (M. DICimtri Cont

17、rol4 channellink 芯片到接插件的位分布4.1 Base, Medium and Full Configurations的位分布芯片端的位分布Pin-NameChip X SignalChip Y SignalChip Z SignalTxCLK Out/ TxCLK InStrobeStrobeStrobeTX/RX24LVALLVALLVALTX/RX25FVALFVALFVALTX/RX26DVALDVALDVALTX/RX23SpareSpareSpareTX/RX0PortA0PortD0PortG0TX/RX1PortA1PortD1PortG1TX/RX2PortA

18、2PortD2PortG2TX/RX3PortA3PortD3PortG3TX/RX4PortA4PortD4PortG4TX/RX6PortA5PortD5PortG5TX/RX27PortA6PortD6PortG6TX/RX5PortA7PortD7PortG7TX/RX7PortB0PortE0PortH0TX/RX8PortB1PortE1PortH1TX/RX9PortB2PortE2PortH2TX/RX12PortB3PortE3PortH3TX/RX13PortB4PortE4PortH4TX/RX14PortB5PortE5PortH5TX/RX10PortB6PortE6

19、PortH6TX/RX11PortB7PortE7PortH7TX/RX15PortC0PortF0TX/RX18PortC1PortF1TX/RX19PortC2PortF2TX/RX20PortC3PortF3TX/RX21PortC4PortF4TX/RX22PortC5PortF5TX/RX16PortC6PortF6TX/RX17PortC7PortF74.2 Bit Allocation for the 80-Bit, 10-tap/8-bitConfiguration芯片端的位分布Pin-NameChip X SignalChip Y SignalChip Z SignalTxC

20、LK Out/ TxCLK InStrobeStrobeStrobeTX/RX0Port A0Port D2Port G5TX/RX1Port A1Port D3Port G6TX/RX2Port A2Port D4Port G7TX/RX3Port A3Port D5Port H0TX/RX4Port A4Port D6Port H1TX/RX5Port A5Port D7Port H2TX/RX6Port A6Port E0Port H3TX/RX7Port A7Port E1Port H4TX/RX8Port B0Port E2Port H5TX/RX9Port B1Port E3Por

21、t H6TX/RX10Port B2Port E4Port H7TX/RX11Port B3Port E5Port I0TX/RX12Port B4Port E6Port I1TX/RX13Port B5Port E7Port I2TX/RX14Port B6Port F0Port I3TX/RX15Port B7Port F1Port I4TX/RX16Port C0Port F2Port I5TX/RX17Port C1Port F3Port I6TX/RX18Port C2Port F4Port I7TX/RX19Port C3Port F5Port J0TX/RX20Port C4Po

22、rt F6Port J1TX/RX21Port C5Port F7Port J2TX/RX22Port C6Port G0Port J3TX/RX23Port C7Port G1Port J4TX/RX24LVALPort G2Port J5TX/RX25FVALPort G3Port J6TX/RX26Port D0Port G4Port J7TX/RX27Port D1LVALLVAL4.3 Bit Allocationfor the 80-Bit, 8-tap/10-bitConfiguration芯片端的位分布Pin-NameChip X SignalChip Y SignalChip

23、 Z SignalTxCLK Out/ TxCLK InStrobeStrobeStrobeTX/RX0Port A0Port D0Port G0TX/RX1Port A1Port D1Port G1TX/RX2Port A2Port D2Port G2TX/RX3Port A3Port D3Port G3TX/RX4Port A4Port D4Port G4TX/RX6Port A5Port D5Port G5TX/RX27Port A6Port D6Port G6TX/RX5Port A7Port D7Port G7TX/RX7Port B0Port E0Port H0TX/RX8Port

24、 B1Port E1Port H1TX/RX9Port B2Port E2Port H2TX/RX12Port B3Port E3Port H3TX/RX13Port B4Port E4Port H4TX/RX14Port B5Port E5Port H5TX/RX10Port B6Port E6Port H6TX/RX11Port B7Port E7Port H7TX/RX15Port C0Port F0Port I5TX/RX18Port C1Port F1Port I6TX/RX19Port C2Port F2Port I7TX/RX20Port C3Port F3Port J0TX/R

25、X21Port C4Port F4Port J1TX/RX22Port C5Port F5Port J2TX/RX16Port C6Port F6Port J3TX/RX17Port C7Port F7Port J4TX/RX24LVALLVALLVALTX/RX25FVALPort I2Port J5TX/RX26Port I0Port I3Port J6TX/RX23Port I1Port I4Port J74.4 Bit Allocation for the Lite Configuration芯片端位分布Pin-NameChip X Signals8-bit10-bitTxCLK Ou

26、t/ TxCLK InStrobeStrobeTX/RX24LVALLVALTX/RX25FVALFVALTX/RX26DVALDVALTX/RX22SerTFGSerTFGTX/RX0PortA0PortA0TX/RX1PortA1PortA1TX/RX2PortA2PortA2TX/RX3PortA3PortA3TX/RX4PortA4PortA4TX/RX6PortA5PortA5TX/RX20PortA6PortA6TX/RX21PortA7PortA7TX/RX7PortB0PortB0TX/RX19PortB1PortB15不同配置的位分布5.1 Bit Assignments f

27、or Base ConfigurationPort/bit8-bit x13*10-bit x 1212-bit x 1214-bit x 116-bit x 124-bit RGBPort A0A0A0A0A0A0R0Port A1A1A1A1A1A1R1Port A2A2A2A2A2A2R2Port A3A3A3A3A3A3R3Port A4A4A4A4A4A4R4Port A5A5A5A5A5A5R5Port A6A6A6A6A6A6R6Port A7A7A7A7A7A7R7Port B0B0A8A8A8A8G0Port B1B1A9A9A9A9G1Port B2B2NcA10A10A1

28、0G2Port B3B3NcA11A11A11G3Port B4B4B8B8A12A12G4Port B5B5B9B9A13A13G5Port B6B6NcB10ncA14G6Port B7B7NcB11ncA15G7Port C0C0B0B0ncncB0Port C1C1B1B1ncncB1Port C2C2B2B2ncncB2Port C3C3B3B3ncncB3Port C4C4B4B4ncncB4Port C5C5B5B5ncncB5Port C6C6B6B6ncncB6Port C7C7B7B7ncncB7*如果使用一个通道，使用 PORTA ,如果使用两个通道使用PARTA和POA

29、RTB5.2 Bit Assignment for Medium ConfigurationPort/bit8-bit x 410-bit x 3412-bit x 3430-bit RGB36-bit RGBPort A0A0A0A0R0R0Port A1A1A1A1R1R1Port A2A2A2A2R2R2Port A3A3A3A3R3R3Port A4A4A4A4R4R4Port A5A5A5A5R5R5Port A6A6A6A6R6R6Port A7A7A7A7R7R7Port B0B0A8A8R8R8Port B1B1A9A9R9R9Port B2B2ncA10ncR10Port B

30、3B3ncA11ncR11Port B4B4B8B8B8B8Port B5B5B9B9B9B9Port B6B6ncB10ncB10Port B7B7ncB11ncB11Port C0C0B0B0B0B0Port C1C1B1B1B1B1Port C2C2B2B2B2B2Port C3C3B3B3B3B3Port C4C4B4B4B4B4Port C5C5B5B5B5B5Port C6C6B6B6B6B6Port C7C7B7B7B7B7Port D0D0D0D0ncncPort D1D1D1D1ncncPort D2D2D2D2ncncPort D3D3D3D3ncncPort D4D4D4

31、D4ncncPort D5D5D5D5ncncPort D6D6D6D6ncncPort D7D7D7D7ncncPort E0NcC0C0G0G0Port E1NcC1C1G1G1Port E2NcC2C2G2G2Port E3NcC3C3G3G3Port E4NcC4C4G4G4Port E5NcC5C5G5G5Port E6NcC6C6G6G6Port E7NcC7C7G7G7Port F0NcC8C8G8G8Port F1NcC9C9G9G9Port F2NcncC10ncG10Port F3NcncC11ncG11Port F4NcD8D8ncncPort F5NcD9D9ncncP

32、ort F6NcncD10ncncPort F7NcncD11ncnc5.3 Bit Assignment for Full/80 bit ConfigurationPort/bit8-bit x 8Port/bit8-bit x 8Port A0A0Port E0E0Port A1A1Port E1E1Port A2A2Port E2E2Port A3A3Port E3E3Port A4A4Port E4E4Port A5A5Port E5E5Port A6A6Port E6E6Port A7A7Port E7E7Port B0B0Port F0F0Port B1B1Port F1F1Por

33、t B2B2Port F2F2Port B3B3Port F3F3Port B4B4Port F4F4Port B5B5Port F5F5Port B6B6Port F6F6Port B7B7Port F7F7Port C0C0Port G0G0Port C1C1Port G1G1Port C2C2Port G2G2Port C3C3Port G3G3Port C4C4Port G4G4Port C5C5Port G5G5Port C6C6Port G6G6Port C7C7Port G7G7Port D0D0Port H0H0Port D1D1Port H1H1Port D2D2Port H

34、2H2Port D3D3Port H3H3Port D4D4Port H4H4Port D5D5Port H5H5Port D6D6Port H6H6Port D7D7Port H7H75.4 Bit Assignments for 80 bit Configuration,10-tap/8-bit mode80bits配置方式支持移动配置 80bits ,在这种模式下，full模式下不用的多余的信号被配置 成携带数据信号。注意：80bit正式名称曾称作" deca "或"full plus ”配置，目前已80bt使用称 80bit 配置有两个版本，10tap/8

35、bit 和 8bit/10tapmode.本节是10tap/8bit 模式PortCameraGrabberSignalPort A0TxIN0RxOUT0D0 Bit 0Port A1TxIN1RxOUT1D0 Bit 1Port A2TxIN2RxOUT2D0 Bit 2Port A3TxIN3RxOUT3D0 Bit 3Port A4TxIN4RxOUT4D0 Bit 4Port A5TxIN5RxOUT5D0 Bit 5Port A6TxIN6RxOUT6D0 Bit 6Port A7TxIN7RxOUT7D0 Bit 7 (MSB)Port B0TxIN8RxOUT8D1 Bit 0

36、Port B1TxIN9RxOUT9D1 Bit 1Port B2TxIN10RxOUT10D1 Bit 2Port B3TxIN11RxOUT11D1 Bit 3Port B4TxIN12RxOUT12D1 Bit 4Port B5TxIN13RxOUT13D1 Bit 5Port B6TxIN14RxOUT14D1 Bit 6Port B7TxIN15RxOUT15D1 Bit 7 (MSB)Port C0TxIN16RxOUT16D2 Bit 0Port C1TxIN17RxOUT17D2 Bit 1Port C2TxIN18RxOUT18D2 Bit 2Port C3TxIN19RxO

37、UT19D2 Bit 3Port C4TxIN20RxOUT20D2 Bit 4Port C5TxIN21RxOUT21D2 Bit 5Port C6TxIN22RxOUT22D2 Bit 6Port C7TxIN23RxOUT23D2 Bit 7 (MSB)LVALTxIN24RxOUT24Line ValidFVALTxIN25RxOUT25Frame ValidPort D0TxIN26RxOUT26D3 Bit 0Port D1TxIN27RxOUT27D3 Bit 1StrobeTxCLKInRxCLKOutPixel ClockPortCameraGrabberSignalPort

38、 D2TxINORxOUTOD3 Bit 2Port D3TxINIRxOUTID3 Bit 3Port D4TxIN2RxOUT2D3 Bit 4Port D5TxIN3RxOUT3D3 Bit 5Port D6TxIN4RxOUT4D3 Bit 6Port D7TxIN5RxOUT5D3 Bit 7 (MSB)Port E0TxIN6RxOUT6D4 Bit 0Port E1TxIN7RxOUT7D4 Bit 1Port E2TxIN8RxOUT8D4 Bit 2Port E3TxIN9RxOUT9D4 Bit 3Port E4TxIN10RxOUT10D4 Bit 4Port E5TxI

39、N11RxOUTIID4 Bit 5Port E6TxIN12RxOUT12D4 Bit 6Port E7TxIN13RxOUT13D4 Bit 7 (MSB)Port F0TxIN14RxOUT14D5 Bit 0Port F1TxIN15RxOUT15D5 Bit 1Port F2TxIN16RxOUT16D5 Bit 2Port F3TxIN17RxOUT17D5 Bit 3Port F4TxIN18RxOUT18D5 Bit 4Port F5TxIN19RxOUT19D5 Bit 5Port F6TxIN20RxOUT20D5 Bit 6Port F7TxIN21RxOUT21D5 B

40、it 7 (MSB)Port G0TxIN22RxOUT22D6 Bit 0Port G1TxIN23RxOUT23D6 Bit 1Port G2TxIN24RxOUT24D6 Bit 2Port G3TxIN25RxOUT25D6 Bit 3Port G4TxIN26RxOUT26D6 Bit 4LVALTxIN27RxOUT27Line ValidStrobeTxCLKInRxCLKOutPixel ClockPortCameraGrabberSignalPort G5TxINORxOUTOD6 Bit 5Port G6TxINIRxOUTID6 Bit 6Port G7TxIN2RxOU

41、T2D6 Bit 7 (MSB)Port H0TxIN3RxOUT3D7 Bit 0Port H1TxIN4RxOUT4D7 Bit 1Port H2TxIN5RxOUT5D7 Bit 2Port H3TxIN6RxOUT6D7 Bit 3Port H4TxIN7RxOUT7D7 Bit 4Port H5TxIN8RxOUT8D7 Bit 5Port H6TxIN9RxOUT9D7 Bit 6Port H7TxIN10RxOUT10D7 Bit 7 (MSB)Port I0TxIN11RxOUTIID8 Bit 0Port I1TxIN12RxOUT12D8 Bit 1Port I2TxIN1

42、3RxOUT13D8 Bit 2Port I3TxIN14RxOUT14D8 Bit 3Port I4TxIN15RxOUT15D8 Bit 4Port I5TxIN16RxOUT16D8 Bit 5Port I6TxIN17RxOUT17D8 Bit 6Port I7TxIN18RxOUT18D8 Bit 7 (MSB)Port J0TxIN19RxOUT19D9 Bit 0Port J1TxIN20RxOUT20D9 Bit 1Port J2TxIN21RxOUT21D9 Bit 2Port J3TxIN22RxOUT22D9 Bit 3Port J4TxIN23RxOUT23D9 Bit

43、 4Port J5TxIN24RxOUT24D9 Bit 5Port J6TxIN25RxOUT25D9 Bit 6Port J7TxIN26RxOUT26D9 Bit 7 (MSB)LVALTxIN27RxOUT27Line ValidStrobeTxCLKInRxCLKOutPixel Clock5.5 Bit Assignments for 80 bit Configuration,8-tap/10-bit modePortCameraGrabberSignalPort A0TxINORxOUTODO Bit 2Port A1TxINIRxOUTIDO Bit 3Port A2TxIN2

44、RxOUT2DO Bit 4Port A3TxIN3RxOUT3DO Bit 5Port A4TxIN4RxOUT4DO Bit 6Port A5TxIN6RxOUT6DO Bit 7Port A6TxIN27RxOUT27DO Bit 8Port A7TxIN5RxOUT5DO Bit 9 (MSB)Port B0TxIN7RxOUT7D1 Bit 2Port B1TxIN8RxOUT8D1 Bit 3Port B2TxIN9RxOUT9D1 Bit 4Port B3TxIN12RxOUT12D1 Bit 5Port B4TxIN13RxOUT13D1 Bit 6Port B5TxIN14R

45、xOUT14D1 Bit 7Port B6TxINIORxOUTIOD1 Bit 8Port B7TxIN11RxOUTIID1 Bit 9 (MSB)Port COTxIN15RxOUT15D2 Bit 2Port C1TxIN18RxOUT18D2 Bit 3Port C2TxIN19RxOUT19D2 Bit 4Port C3TxIN20RxOUT2OD2 Bit 5Port C4TxIN21RxOUT21D2 Bit 6Port C5TxIN22RxOUT22D2 Bit 7Port C6TxIN16RxOUT16D2 Bit 8Port C7TxIN17RxOUT17D2 Bit 9 (MSB)LVALTxIN24RxOUT24Line ValidFVALTxIN25RxOUT25Frame ValidPort I0TxIN26RxOUT26D0