数字电路实验报告——交通灯控制器(VHDL).doc

1、 数字电路与逻辑设计实验报告学院：信通院 班级：2008211126 姓名：王寻 学号：08210712 班内序号：16一、实验课题交通灯控制器二、任务要求 设计制作一个用于十字路口的交通灯控制器。南北和东西方向各有一组绿、黄、红灯用于指挥交通，绿灯、黄灯和红灯的持续时间分别为20 秒、5 秒和25 秒； 当有特殊情况（如消防车、救护车等）时，两个方向均为红灯亮，计时停止，当特殊情况结束后，控制器恢复原来状态，继续正常运行； 用两组数码管，以倒计时方式显示两个方向允许通行或禁止通行的时间； ·选做：增加左、右转弯显示控制功能； ·选做：其它自拟功能。三、设计思路 利用有限状

2、态机描绘出交通灯的状态转移图，并设置记录东西和南北路口可通行时间的全局变量count1，count2。状态间的转移以count1，count2的值作为判断条件。对于两种特殊情况：当复位信号reset为高电平时，则回到最初状态；当紧急输入信号emergency为高电平时，则转移到一特殊状态。四、总体框图及分块设计1.实验的总体框图如下所示交通灯控制器逻辑划分方框图交通灯控制器逻辑流程图交通灯控制器的状态转移图 其中图中count1和count2分别是南北方向和东西方向交通灯允许或禁止通行的时间，程序已将南北方向和东西方向的交通灯分别初始化为绿灯和红灯，count1和count2分别初始化为20和

3、25。一般情况下在一个时钟周期后count1和count2 的值都将减1。另外，在reset信号为高电平时，不论其他状态和信号如何，系统回到S0状态且count1和count2的值分别为20和25，在reset信号为低电平且emergency为高电平时，两个方向交通灯均为红灯且其数码管均显示0，直到emergency恢复低电平时，系统恢复到emergency刚快要出现时系统的状态，并重新正常运行。由于考虑了reset和emergency这两个特殊输入信号后，状态转移图将会变得很复杂且不易画出，故在此略去这两个特殊输入信号。在我的实验设计中，整个交通灯控制器包括5个模块：控制器模块control

4、；计数模块countdown；主分频模块fenpin；为数码管共阴极扫描电压产生扫描频率的分频模块showfenpin；数码管显示译码模块show。现对各个模块的设计作一简要阐述：控制器模块control：这是整个程序的核心模块，控制着交通灯状态的转移和交通灯通行时间count1和count2数值的改变，该模块是交通灯状态转移图的程序实现。计数模块countdown：该模块将count1和count2数值转化为二进制信号并以较高频率扫描数码管的共阴极以显示多位数字的通行时间，是一个初级译码模块。主分频模块fenpin：该模块将实验板固有50M晶振时钟频率进行50000000分频，以产生控制器模

5、块所需的1Hz频率。为数码管共阴极扫描电压产生扫描频率的分频模块showfenpin：该模块将实验板固有50M晶振时钟频率进行5000分频，以产生计数模块countdown所需的10kHz频率。(实验中我已尝试过直接用50M晶振的频率直接扫描数码管共阴极，但数码管无法正常显示，将其频率降低一定倍数后数码管方能正常显示)数码管显示译码模块show：该模块通过对每一位数字进行7段数码管译码以显示该数字，实际上我在实验中用的是8位信号。因为7段数码管实际上有8个输出信号，除了7段数码管，还有小数点显示信号。我在实验中设置8位信号并始终置最低位为0，这样可以使数码管不显示小数点，使显示的数字更为美观。

6、五、仿真波形及波形分析以下是我的程序中几个关键部分的仿真波形图(由于这只是仿真，我在程序中只用了一个分频模块fenpin，且为10分频，分频后的输出作为控制器模块的时钟信号，数码管共阴极的扫描频率与外部时钟clk的频率一致):reset和emergency信号均为低电平时light1(南北方向交通灯)和light2(东西方向交通灯)的仿真波形图reset信号为低电平，emergency信号为高电平时light1和light2的仿真波形图reset信号为低电平且emergency信号由高电平降到低电平后light1和light2的仿真波形图reset信号为高电平时light1和light2的仿真

7、波形图reset和emergency信号均为低电平时num(七段数码显示管信号)和cat_tmp(数码管共阴极扫描信号)的仿真波形图reset信号为低电平，emergency信号为高电平时num和cat_tmp的仿真波形图reset信号为低电平且emergency信号由高电平降到低电平后num和cat_tmp的仿真波形图reset信号为高电平时num和cat_tmp的仿真波形图对波形图：根据状态转移图，此时light1和light2的状态应依次由001/100à010/100à100/001à100/010à001/100这样循环变化，波形图中恰好反映了

8、这种变化方式。对波形图：根据emergency信号的特点，此时light1和light2的状态应该均为100，波形图中恰好是反映了这种情况。对波形图：根据本程序设计的思路，emergency信号由高电平变为低电平时light1和light2应回到emergency高电平即将要出现时的状态，由波形图可知当时light1和light2的状态分别为001，100。由此图也可知emergency刚由高电平变为低电平时light1和light2的状态仍分别为001，100。故此时light1和light2的状态符合我的程序设计的思路。对波形图根据reset信号的特点，此时light1和light2应各自

9、回到最初的状态001，100。此时波形图中light1和light2的状态恰好为此种状态。对波形图数码管显示信号num和数码管共阴极扫描信号cat_tmp的变化频率应和时钟信号clk的频率一致，且cat_tmp信号变化规律为：0111111à101111à111101à111110à0111111这样循环变化(下同)，波形图中num和cat_tmp信号变化频率与此相符，且cat_tmp信号变化规律也与此相符数码管的信号翻译成数字序列即为：20252024，结合cat_tmp的变化规律可知此时数码管实现了各位数字的扫描显示。对波形图此时num信号应一直为0

10、，即11111100，波形图中的num信号恰好是这种情况。对波形图根据本程序设计的思路，emergency信号由高电平变为低电平时num应回到emergency高电平即将要出现时的状态，由波形图可知当时num输出的数字序列为012025即两数码管应分别显示20，25。由此图也可知emergency刚由高电平变为低电平时num输出的数字序列为20252025，即两数码管分别显示20，25，符合最初我的程序设计思路。对波形图 根据reset信号的特点，此时num应回到最初状态，分别显示20和25，此时波形图中num对应输出数字序列为20252025，符合reset的信号特点。六、源程序本实验的源程

11、序如下主程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity traffic isport( clk,reset,emergency:in std_logic; -定义时钟，复位和紧急情况输入信号 light1,light2:out std_logic_vector(2 downto 0); -定义交通灯状态输出信号 cat_tmp:out std_logic_vector(5 downto 0); -定义数码管共阴极扫描信号

12、num:out std_logic_vector(7 downto 0); -定义数码管输出信号end traffic;architecture trafficlight of traffic issignal tmp_clk:std_logic;signal tmp_showclk:std_logic;signal tempcount1:std_logic_vector(5 downto 0);signal tempcount2:std_logic_vector(5 downto 0);signal tempnum:std_logic_vector(3 downto 0);signal si

13、nglenum:std_logic_vector(3 downto 0);component fenpin is -主分频模块port( clk:in std_logic; clk_out:out std_logic);end component;component showfenpin is -为数码管共阴极扫描提供扫描频率的分频模块port( clk:in std_logic; clk_out:out std_logic);end component;component control is -控制器模块port(clk:in std_logic; emergency:in std_log

14、ic; reset:in std_logic; light1:out std_logic_vector(2 downto 0); light2:out std_logic_vector(2 downto 0); counter1,counter2:out std_logic_vector(5 downto 0);end component;component countdown is -计数器模块port(clk:in std_logic; cat_tmp:out std_logic_vector(5 downto 0); numin:out std_logic_vector(3 downto

15、 0); emergency:in std_logic; reset:in std_logic; counter1,counter2:in std_logic_vector(5 downto 0);end component;component show is -数码管显示译码模块port(num_in:in std_logic_vector(3 downto 0); num:out std_logic_vector(7 downto 0);end component;begin -将各模块的接口连接在一起，构成系统总线u1:fenpin port map(clk=>clk,clk_ou

16、t=>tmp_clk);u2:showfenpin port map(clk=>clk,clk_out=>tmp_showclk);u3:control port map(clk=>tmp_clk,emergency=>emergency,reset=>reset,counter1=>tempcount1,counter2=>tempcount2,light1=>light1,light2=>light2);u4:countdown port map(clk=>tmp_showclk,cat_tmp=>cat_tmp,co

17、unter1=>temp-count1,counter2=>tempcount2,numin=>singlenum,emergency=>emergency,reset=>re-set);u5:show port map(num_in=>singlenum,num=>num);end trafficlight;分频模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport( clk:in std_logic; -定义输入时

18、钟信号 clk_out:out std_logic); -定义输出时钟信号end fenpin;architecture at of fenpin is signal tmp:integer range 0 to 49999999; begin p1:process(clk) begin if clk'event and clk='1' then -每50000000个时钟周期作为一个新的周 if tmp=49999999 then tmp<=0; -期，且该周期前半部分(tmp<25000000时) else tmp<=tmp+1; -输出为高电平，

19、后半部分输出为高电平， end if; -从而实现对时钟信号的50000000分频 if tmp<25000000 then clk_out<='0' else clk_out<='1' end if; end if; end process p1;end at;为数码管共阴极扫描提供扫描频率的分频模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity showfenpin isport( clk:in std_logic; -定义输入时

20、钟信号 clk_out:out std_logic); -定义输出时钟信号end showfenpin;architecture at of showfenpin is signal tmp:integer range 0 to 4999; begin -每5000个时钟周期作为一个新的周 p1:process(clk) -期，且该周期前半部分(tmp<2500时) begin -输出为高电平，后半部分输出为高电平， if clk'event and clk='1' then -从而实现对时钟信号的5000分频 if tmp=4999 then tmp<=0

21、; else tmp<=tmp+1; end if; if tmp<2500 then clk_out<='0' else clk_out<='1' end if; end if; end process p1;end at;控制器模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity control isport(clk:in std_logic; -定义输入时钟、紧急、复

22、位信号 emergency:in std_logic; reset:in std_logic; light1:out std_logic_vector(2 downto 0):="001" -定义交通灯状态信号 light2:out std_logic_vector(2 downto 0):="100" counter1:out std_logic_vector(5 downto 0); -定义计数变量count1，count2 counter2:out std_logic_vector(5 downto 0);end control;architect

23、ure arch of control is signal count1:integer:=20; signal count2:integer:=25; signal templight1: std_logic_vector(2 downto 0):="001" signal templight2: std_logic_vector(2 downto 0):="100" type all_state is (s0,s1,s2,s3,s4); -定义状态机all_state，包含s0,s1,s2,s3,s4共5 signal state:all_state

24、:=s0; -个状态，并初始化为状态s0 signal tempstate:all_state:=s0;begin p2:process(clk,emergency,reset) begin if (reset='1') then state<=s0;count1<=20;count2<=25;light1<="001"light2<="100"templight1<="001"templight2<="100" elsif (emergency ='

25、;1') then state<=s4;light1<="100"light2<="100" elsif (clk'event and clk='1') then case state is when s0=> if count1>1 then count1<=count1-1;count2<=count2-1;tempstate<=s0; else state<=s1;tempstate<=s1;count1<=5;light1<="010

26、"light2<="100"templight1<="010"templight2<="100" end if;when s1=> if count1>1 then count1<=count1-1;count2<=count2-1;tempstate<=s1; else state<=s2;tempstate<=s2;count1<=25;count2<=20;light1<="100"light2<="001

27、"templight1<="100"templight2<="001" end if; when s2=> if count2>1 then count1<=count1-1;count2<=count2-1;tempstate<=s2; else state<=s3;tempstate<=s3;count2<=5;light1<="100"light2<="010"templight1<="100"temp

28、light2<="010" end if; when s3=> if count2>1 then count1<=count1-1;count2<=count2-1;tempstate<=s3; else state<=s0;tempstate<=s0;count1<=20;count2<=25;light1<="001"light2<="100"templight1<="001"templight2<="100"

29、; end if; when s4=> state<=tempstate;light1<=templight1;light2<=templight2; when others=> state<=s0;tempstate<=s0;count1<=20;count2<=25;light1<="001"light2<="100"templight1<="001"templight2<="100" end case; end if;end pro

30、cess p2;counter1<=conv_std_logic_vector(count1,6);counter2<=conv_std_logic_vector(count2,6);end arch;-以上一段代码为本程序中最关键的一部分，它是整个程序的控制中枢。计数变-量count1和count2被初始化为20和25，状态机被初始化为s0状态。对于此-时的特殊输入：reset和emergency，我给reset分配了更高的优先级，emergency-次之，即reset=1时，不论其他输入和输出如何，系统回到s0状态，且count1-和count2的值回到20和25，当reset

31、=0且emergency=1时，系统转入紧急状态s4，-此时light1和light2都为100(红灯)状态。当reset和emergency均为0时，系统正常-运行，一般情况下count1和count2在每遇到一个时钟周期后各减1。在状态s0中，-当count1的值大于1时count1和count2各减1；当count1=1时，转入s1状态，light1-和light2分别为黄灯和红灯状态，且count1被置为5。接着在状态s1中，当count1-的值大于1时count1和count2各减1；当count1=1时，转入s2状态，light1和light2-分别为红灯和绿灯状态，且count1

32、被置为25，count2被置为20。接着在状态s2-中，当count2的值大于1时count1和count2各减1；当count2=1时，转入s3状态，-light1和light2分别为红灯和黄灯状态，且count2被置为5。接着在状态s3中，当-count2的值大于1时count1和count2各减1；当count2=1时，转入s0状态。程序就-这样周而复始地运行下去。为了保证在emergency信号消失后，我在程序中特地-设定了存储当前交通灯状态的信号templight1和templight2，分别记录light1和-light2的状态，以及存储当前状态机状态的信号tempstate。在e

33、mergency信号为-高电平时，系统进入s4状态。在非s4状态时，每遇到一个时钟沿，程序给-templight1和templight2分别赋以和light1和light2相同的状态，给tempstate也赋以-和state相同的状态。这样在状态机状态为s4时，light1和light2以及state分别为-templight1、templight2、和tempstate的值，此时系统回到了紧急信号出现前的-状态。计数器模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_

34、logic_arith.all;entity countdown isport(clk:in std_logic; -定义输入时钟信号 cat_tmp:out std_logic_vector(5 downto 0);-定义数码管共阴极扫描输出信号 numin:out std_logic_vector(3 downto 0); -定义输出数字信号 emergency:in std_logic; -定义输入紧急信号 reset:in std_logic; -定义输入复位信号 counter1:in std_logic_vector(5 downto 0); -定义南北方向交通灯计数变量 coun

35、ter2:in std_logic_vector(5 downto 0); -定义东西方向交通灯计数变量end countdown;architecture arch of countdown issignal temp:integer range 0 to 3;signal count1:integer range 0 to 25;signal count2:integer range 0 to 25;signal count:integer range 0 to 25;signal num_in:std_logic_vector(3 downto 0);signal cat:std_log

36、ic_vector(5 downto 0):="011111"begin p1:process(clk)begincount1<=conv_integer(counter1); count2<=conv_integer(counter2); if(clk'event and clk='1') then if(temp=3) then temp<=0; else temp<=temp+1; -使temp实现03的计数功能 end if; end if;end process p1;p2:process(temp) begin c

37、ase temp is when 0=> count<=count1; -temp值变化的前半周期count被赋值count1 when 1=> count<=count1; when 2=> count<=count2; -temp值变化的前半周期count被赋值coun2 when 3=> count<=count2; end case; end process p2; p3:process(count,temp,emergency,reset) begin if(reset='0' and emergency='1&

38、#39;) then -无复位信号且有紧急信号使数码管均显示1 case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="0000"cat<="101111" when 2=> num_in<="0000"cat<="111101" when 3=> num_in<="0000"cat<="1111

39、10" end case; else case count is when 0=>case temp is when 0=> num_in<="0000"cat<="011111" -cat为数码管共阴极输出信号， when 1=> num_in<="0000"cat<="101111" -表示当前时刻那个数码管有效， when 2=> num_in<="0000"cat<="111101"-temp从0到

40、3时，num_in对应 when 3=> num_in<="0000"cat<="111110"-的信号值分别为count数值的高 end case; -位、低位、高位、低位，下同。 when 1=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="0001"cat<="101111" when 2=> num_in<=

41、"0000"cat<="111101" when 3=> num_in<="0001"cat<="111110" end case; when 2=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="0010"cat<="101111" when 2=> num_in<=&q

42、uot;0000"cat<="111101" when 3=> num_in<="0010"cat<="111110" end case; when 3=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="0011"cat<="101111" when 2=> num_in<=&quo

43、t;0000"cat<="111101" when 3=> num_in<="0011"cat<="111110" end case; when 4=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="0100"cat<="101111" when 2=> num_in<="

44、0000"cat<="111101" when 3=> num_in<="0100"cat<="111110" end case; when 5=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="0101"cat<="101111" when 2=> num_in<="00

45、00"cat<="111101" when 3=> num_in<="0101"cat<="111110" end case; when 6=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="0110"cat<="101111" when 2=> num_in<="0000

46、"cat<="111101" when 3=> num_in<="0110"cat<="111110" end case; when 7=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="0111"cat<="101111" when 2=> num_in<="0000&q

47、uot;cat<="111101" when 3=> num_in<="0111"cat<="111110" end case; when 8=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="1000"cat<="101111" when 2=> num_in<="0000&quo

48、t;cat<="111101" when 3=> num_in<="1000"cat<="111110" end case; when 9=>case temp is when 0=> num_in<="0000"cat<="011111" when 1=> num_in<="1001"cat<="101111" when 2=> num_in<="0000"

49、cat<="111101" when 3=> num_in<="1001"cat<="111110" end case; when 10=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="0000"cat<="101111" when 2=> num_in<="0001"c

50、at<="111101" when 3=> num_in<="0000"cat<="111110" end case; when 11=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="0001"cat<="101111" when 2=> num_in<="0001"ca

51、t<="111101" when 3=> num_in<="0001"cat<="111110" end case; when 12=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="0010"cat<="101111" when 2=> num_in<="0001"cat

52、<="111101" when 3=> num_in<="0010"cat<="111110" end case; when 13=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="0011"cat<="101111" when 2=> num_in<="0001"cat&

53、lt;="111101" when 3=> num_in<="0011"cat<="111110" end case; when 14=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="0100"cat<="101111" when 2=> num_in<="0001"cat&l

54、t;="111101" when 3=> num_in<="0100"cat<="111110" end case; when 15=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="0101"cat<="101111" when 2=> num_in<="0001"cat<

55、;="111101" when 3=> num_in<="0101"cat<="111110" end case; when 16=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="0110"cat<="101111" when 2=> num_in<="0001"cat<

56、="111101" when 3=> num_in<="0110"cat<="111110" end case; when 17=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="0111"cat<="101111" when 2=> num_in<="0001"cat<=

57、"111101" when 3=> num_in<="0111"cat<="111110" end case; when 18=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="1000"cat<="101111" when 2=> num_in<="0001"cat<=&

58、quot;111101" when 3=> num_in<="1000"cat<="111110" end case; when 19=>case temp is when 0=> num_in<="0001"cat<="011111" when 1=> num_in<="1001"cat<="101111" when 2=> num_in<="0001"cat<=&q

59、uot;111101" when 3=> num_in<="1001"cat<="111110" end case; when 20=>case temp is when 0=> num_in<="0010"cat<="011111" when 1=> num_in<="0000"cat<="101111" when 2=> num_in<="0010"cat<=&qu

60、ot;111101" when 3=> num_in<="0000"cat<="111110" end case; when 21=>case temp is when 0=> num_in<="0010"cat<="011111" when 1=> num_in<="0001"cat<="101111" when 2=> num_in<="0010"cat<=&quo

61、t;111101" when 3=> num_in<="0001"cat<="111110" end case; when 22=>case temp is when 0=> num_in<="0010"cat<="011111" when 1=> num_in<="0010"cat<="101111" when 2=> num_in<="0010"cat<="

62、;111101" when 3=> num_in<="0010"cat<="111110" end case; when 23=>case temp is when 0=> num_in<="0010"cat<="011111" when 1=> num_in<="0011"cat<="101111" when 2=> num_in<="0010"cat<="

63、111101" when 3=> num_in<="0011"cat<="111110" end case; when 24=>case temp is when 0=> num_in<="0010"cat<="011111" when 1=> num_in<="0100"cat<="101111" when 2=> num_in<="0010"cat<="1

64、11101" when 3=> num_in<="0100"cat<="111110" end case; when 25=>case temp is when 0=> num_in<="0010"cat<="011111" when 1=> num_in<="0101"cat<="101111" when 2=> num_in<="0010"cat<="111101" when 3=> num_in<="0101"cat<="