FPGA轨道交通自动售票电路

1、设计一个轨道交通自动售票电路，只接受1，2，5元人民币，每张票价定额5元，并支持找零。要求：(1)用状态机方法设计；(2)用VerilogHDL语言设计，用Modelsim软件做功能仿真，用QuartusII综合。(3)将设计代码和仿真代码写在作业本上。modulezhaoling(clock,reset,A,ticket,change);inputclock,reset;input2:0A;outputticket;output2:0change;reg2:0state;regticket;reg2:0change;parametersta_0=3'd0,sta_1=3'd1

2、,sta_2=3'd2,sta_3=3'd3,sta_4=3'd4,sta_5=3'd5;always(posedgeclockornegedgereset)if(!reset)beginstate<=sta_0;ticket<=0;change<=0;endelsecase(state)sta_0:if(A=1)beginstate=sta_1;ticket<=0;change<=0;endelseif(A=2)beginstate=sta_2;ticket<=0;change<=0;endelseif(A=5)beg

3、instate=sta_5;ticket<=1;change<=0;endelsebeginstate=sta_0;ticket<=0;change<=0;endsta_1:if(A=1)beginstate=sta_2;ticket<=0;change<=0;endelseif(A=2)beginstate<=sta_3;ticket<=0;change<=0;endelseif(A=5)beginstate<=sta_O;ticket<=1;change<=1;endelsebeginstate<=sta_1;t

4、icket<=0;change<=0;endsta_2:if(A=1)beginstate<=sta_3;ticket<=0;change<=0;endelseif(A=2)beginstate<=sta_4;ticket<=0;change<=0;endelseif(A=5)beginstate<=sta_O;ticket<=1;change<=2;endelsebeginstate<=sta_2;ticket<=0;change<=0;endsta_3:if(A=1)beginstate<=sta_4

5、;ticket<=0;change<=0;endelseif(A=2)beginstate<=sta_5;ticket<=1;change<=0;endelseif(A=5)beginstate<=sta_5;ticket<=1;change<=3;endelsebeginstate<=sta_3;ticket<=0;change<=0;endsta_4:if(A=1)beginstate<=sta_5;ticket<=1;change<=0;endelseif(A=2)beginstate<=sta_5

6、;ticket<=1;change<=1;endelseif(A=5)beginstate<=sta_5;ticket<=1;change<=4;endelsebeginstate<=sta_4;ticket<=0;change<=0;endsta_5:if(A=1)beginstate<=sta_1;ticket<=0;change<=0;endelseif(A=2)beginstate<=sta_2;ticket<=0;change<=0;endelseif(A=5)beginstate<=sta_5

7、;ticket<=1;change<=0;endelsebeginstate<=sta_5;ticket<=0;change<=0;enddefault:state<=sta_O;endcaseendmoduletimescale1ns/1nsmoduletest;regClock,Reset;reg2:0A;wireTicket;wire2:0Change;initialbeginA=0;Reset=1;Clock=0;Reset=0;# 10Reset=1;endalways#10Clock<=Clock;initialbegin# 20A=1;# 20A=1;# 20A=1;# 20A=1;# 20A=1;# 20A=1;# 20A=2;# 20A=2;# 20A=2;# 20A=2;# 20A=1;# 20A=2;# 20A=1;# 20A=2;# 20A=2;# 20A=2;# 20A=2;# 20A=5;endzhao