数电VHDL代码-七段数码管译码器-表决器-半加器-全加器-四位串型加法器

1、七段数码管译码器library ieee;entity seg7_1 isport(a: in std_logic_vector(3 downto 0;b: out std_logic_vector(6 downto 0;end entity seg7_1;architecture one of seg7_1 isbegin process(abegin case a iswhen"0000" => b<="1111110"when"0001" => b<="0110000"when&quo

2、t;0010" => b<="1101101"when"0011" => b<="1111001"when"0100" => b<="0110011"when"0101" => b<="1011011"when"0110" => b<="1011111"when"0111" => b<="0001111&q

3、uot;when"1000" => b<="1111111"when"1001" => b<="1111011"when others => b<="0000000"end case;end process;end ;表决器library ieee;entity vote isport(I: in std_logic_vector(3 downto 0;Y: out std_logic;end entity vote;architecture one of v

4、ote isbeginY<=(I(2 and I(1 and I(0 or (I(3 and I(2 and I(0 or (I(3 and I(1 and I(0 or (I(3 and I(2 and I(1;end one;半加器library ieee;entity hadder isport(a,b: in std_logic;s,co: out std_logic;end entity hadder;architecture one of hadder isbegins<=a xor b;co<=a and b;end one;全加器library ieee;en

5、tity fadder isport(ain,bin,cin: in std_logic;cout,sum: out std_logic;end entity fadder;architecture one of fadder iscomponent hadderport(a,b:in std_logic;co,s:out std_logic;end component ;signal d,e,f:std_logic;beginu1:hadder port map (a=>ain,b=>bin,co=>d,s=>e; u2:hadder port map (a=>

6、e,b=>cin,co=>f,s=>sum; cout<=d or f;end;四位串型加法器library ieee;entity adder4 isport(A,B: in std_logic_vector(3 downto 0;M: in std_logic;R:in std_logic;S: out std_logic_vector(3 downto 0;C: out std_logic;end entity adder4;architecture a of adder4 iscomponent fadderport(ain,bin,cin:in std_log

7、ic;cout,sum:out std_logic;end component ;signal D,F:std_logic_vector(3 downto 0;beginD(0<=M xor B(0;D(1<=M xor B(1;D(2<=M xor B(2;D(3<=M xor B(3;F(0<=M xor R;u1:fadder port map (ain=>A(0,bin=>D(0,cin=>F(0,cout=>F(1,sum=>S(0; u2:fadder port map (ain=>A(1,bin=>D(1,cin=>F(1,cout=>F(2,sum=>S(1; u3:fadder port map (ain=>A(2,bin=>D(2,cin=&g