EDA技术与应用讲义第2章EDA设计流程及其工具ppt课件

1、第第2章章 EDA设计流程及其工具设计流程及其工具 课程讲义课程讲义合肥工业大学 彭良清本章内容vEDA设计的普通步骤v常用EDA工具软件v运用MAX+PLUS II软件设计过程v运用Quartus II软件设计过程v硬件设计和软件设计的时间协调v设计的几个问题EDA设计的普通步骤v电路的模块划分v设计输入v器件和引脚指配v编译与排错v功能仿真和时序仿真v编程与配置，设计代码的芯片运转电路的模块划分v人工人工 根据电路功能根据电路功能 进展进展 模块划分模块划分v合理的模块划分合理的模块划分 关系到关系到v电路的性能电路的性能v实现的难易程度实现的难易程度v根据模块划分和系统功能根据模块划分和

2、系统功能 确定：确定：v PLD芯片型号芯片型号v模块划分后，就可以进展模块划分后，就可以进展 详细设计详细设计 了了设计输入普通EDA软件允许3种设计输入：HDL言语电路图波形输入何为 ？ 器件和引脚指配v器件指配v为设计输入 选择适宜的PLD器件型号v何谓引脚指配v将设计代码图形中的端口PORT 和v PLD芯片的引脚 PINv 对应起来的.v指配文件vMAX+PLUS II： “ *.acf vQuartus II： “ *.qsf 器件和引脚指配的方法方法有2种在软件的菜单界面中指配修正指配文件是文本文件菜单界面中指配修正指配文件vCHIP io_2d_lockvBEGINv|iVD

3、:INPUT_PIN = 7;v|iHD :INPUT_PIN = 8;v|iDENA :INPUT_PIN = 6;v|iCLK : INPUT_PIN = 211;v|oCLK : OUTPUT_PIN = 237;v|oVD :OUTPUT_PIN = 234;v|oHD : OUTPUT_PIN = 233;v|oDENA :OUTPUT_PIN = 235;v.vDEVICE = EPF10K30AQC240-2;vEND;v.编译与排错编译过程有2种，作用分别为：语法编译：只是综合并输出网表编译设计文件，综合产生门级代码编译器只运转到综合这步就停顿了编译器只产生估算的延时数值完全的

4、编译：包括编译，网表输出，综合，配置器件编译器除了完成以上的步骤，还要将设计配置到ALTERA的器件中去编译器根据器件特性产生真正的延时时间和给器件的配置文件功能仿真和时序仿真v仿真的概念：v在设计代码下载到芯片前，在EDA软件中对设计的输出进展波形仿真。v常用的2种仿真方式v功能仿真v对设计的逻辑功能进展仿真v时序仿真v对设计的逻辑功能和信号的时间延时进展仿真。v仿真前还要做的任务v输入信号的建立Quartus II软件中软件中关于仿真的原文关于仿真的原文2种 仿真文件v矢量波形文件： v a Vector Waveform File (.vwf)v文本矢量文件v a text-based

5、Vector File (.vec),编程与配置最后，最后， 假设仿真假设仿真 也正确也正确 的话，的话， 那我们就可以那我们就可以 将设计代码将设计代码 配置或者编程配置或者编程 到到 芯片芯片 中了中了编程的文件类型编程的文件类型对于对于CPLD或者或者EPC2，ECS1等配置芯片，编程文件扩展名为：等配置芯片，编程文件扩展名为：“ *.POF “配置的文件类型配置的文件类型对于对于FPGA芯片，配置文件扩展名为：芯片，配置文件扩展名为：“ *.SOF “硬件设计和软件设计的时间协调v软件模块划分，器件的初步信号确定主要是根据需求的I/O引脚的数量v软件设计，硬件外围电路设计和器件选择 v

6、软件仿真v仿真完成后，器件信号的重新审核，进展硬件电路图设计v综合调试v完成设计的几个问题v如何组织多个设计文件的系统？，工程的概念。v时钟系统如何设计？v电路的设计功耗v高速信号的软件和硬件设计The end.以下内容为正文的援用，可不阅读。常用EDA工具软件vEDA软件方面，大体可以分为两类：vPLD器件厂商提供的EDA工具。较著名的如：vAltera公司的 Max+plus II和Quartus II、vXilinx公司的Foundation Series、vLatice-Vantis公司的ispEXERT System。v第三方专业软件公司提供的EDA工具。常用的有：vSynopsys

7、公司的FPGA Compiler II、vExemplar Logic公司的LeonardoSpectrum、vSynplicity公司的Synplify。v第三方工具软件是对CPLD/FPGA消费厂家开发软件的补充和优化，如通常以为Max+plus II和Quartus II对VHDL/Verilog HDL逻辑综合才干不强，假设采用公用的HDL工具进展逻辑综合，会有效地提高综合质量。ALTERA 公司的公司的EDA协作同伴协作同伴 硬件描画言语：来源v是电子电路的文本描画。v最早的发明者：美国国防部，VHDL,1983v大浪淘沙，为大者二：vVHDL 和 Verilog HDLv其他的小兄

8、弟：vABEL、AHDL、System Verilog、System C。一个D触发器的VHDL代码例子v- VHDL code position: p83_ex4_11_DFF1v-v- LIBARY IEEE;v- USE IEEE.STD_LOGIC_1164.ALL;vENTITY DFF1 IS vPORT (CLK:INBIT;vD:INBIT;vQ:OUTBITv);vEND ENTITY DFF1;vARCHITECTURE bhv OF DFF1 ISvBEGINvPROCESS(CLK)vBEGINvIF CLKEVENT AND (CLK=1) AND ( CLKLAST

9、_VALUE = 0) THENv- 严厉的CLK信号上升沿定义vQ Compiler Netlist Extractor编译器网表提取器编译器网表提取器vThe Compiler module that converts each design file in a project (or each cell of an EDIF Input File) into a separate binary CNF. The filename(s) of the CNF(s) are based on the project name. ExamplevThe Compiler Netlist Ext

10、ractor also creates a single HIF that documents the hierarchical connections between design files.vThis module contains a built-in EDIF Netlist Reader, Verilog Netlist Reader, VHDL Netlist Reader, and converters that translate ADFs and SMFs for use with MAX+PLUS II. vDuring netlist extraction, this

11、module checks each design file for problems such as duplicate node names, missing inputs and outputs, and outputs that are tied together.v前往Database Builder(数据库构建器 ):vThe Compiler module that builds a single, fully flattened project database that integrates all the design files in a project hierarch

12、y. vThe Database Builder uses the HIF to link the CNFs that describe the project. Based on the HIF data, the Database Builder copies each CNF into the project database. Each CNF is inserted into the database as many times as it is used within the original hierarchical project. The database thus pres

13、erves the electrical connectivity of the project.vThe Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the fully optimized project. In the beginning, the database contains only the original netlists; at the en

14、d, it contains a fully minimized, fitted project, which the Assembler uses to create one or more files for device programming. vAs it creates the database, the Database Builder examines the logical completeness and consistency of the project, and checks for boundary connectivity and syntactical erro

15、rs (e.g., a node without a source or destination). Most errors are detected and can be easily corrected at this stage of project processing.v前往Logic SynthesizervThe Compiler module that synthesizes the logic in a projects design files. vUsing the database created by the Database Builder, the Logic S

16、ynthesizer calculates Boolean equations for each input to a primitive and minimizes the logic according to your specifications. vFor projects that use JK or SR flipflops, the Logic Synthesizer checks each case to determine whether a D or T flipflop will implement the project more efficiently. D or T

17、 flipflops are substituted where appropriate, and the resulting equations are minimized accordingly.vThe Logic Synthesizer also synthesizes equations for flipflops to implement state registers of state machines. An equation for each state bit is optimally implemented with either a D or T flipflop. I

18、f no state bit assignments have been made, or if an incomplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the state machine. These encodings are chosen to minimize the resources used.v前往Fitter适配器vThe Compiler module that f

19、its the logic of a project into one or more devices. vUsing the database updated by the Partitioner, the Fitter matches the logic requirements of the project with the available resources of one or more devices. It assigns each logic function to the best logic cell location and selects appropriate in

20、terconnection paths and pin assignments.vThe Fitter attempts to match any resource assignments made for the project with the resources on the device. If it cannot find a fit, the Fitter allows you to override some or all of your assignments or terminate compilation.vThe Fitter module generates a Fit

21、 File that documents pin, buried logic cell, chip, clique, and device assignments made by the Fitter module in the last successful compilation. Each time the project compiles successfully, the Fit File is overwritten. You can back-annotate the assignments in the file to preserve them in future compi

22、lations. v前往Timing SNF Extractor(时序SNF文件提取器)vThe Compiler module that creates a timing SNF containing the logic and timing information required for timing simulation, delay prediction, and timing analysis.vThe Timing SNF Extractor is turned on with the Timing SNF Extractor command (Processing menu).

23、 It is also turned on automatically when you turn on the EDIF Netlist Writer, Verilog Netlist Writer, or VHDL Netlist Writer command (Interfaces menu). The Timing SNF Extractor cannot be turned on at the same time as the Functional SNF Extractor or the Linked SNF Extractor.vA timing SNF describes th

24、e fully optimized circuit after all logic synthesis and fitting have been completed. Regardless of whether a project is partitioned into multiple devices, the timing SNF describes a project as a whole. Therefore, timing simulation and timing analysis (including delay prediction) are available only f

25、or the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional testing is available only for a single-device project.v前往Assembler汇编器vThe Compiler module that creates one or more programming files for programming o

26、r configuring the device(s) for a project. vThe Assembler module completes project processing by converting the Fitters device, logic cell, and pin assignments into a programming image for the device(s), in the form of one or more POFs, SOFs, Hex Files, TTFs, Jam Files, JBC Files, and/or JEDEC Files

27、. POFs and JEDEC Files are always generated; SOFs, Hex Files, and TTFs are always generated if the project uses ACEX 1K, FLEX 6000, FLEX 8000 or FLEX 10K devices; and Jam Files and JBC Files are always generated for MAX 9000, MAX 7000B, MAX 7000AE or MAX 3000A projects. If you turn on the Enable JTA

28、G Support option in the Classic & MAX Global Project Device Options dialog box (Assign menu) or the Classic & MAX Individual Device Options dialog box, the Assembler will also generate Jam Files and JBC Files for MAX 7000A or MAX 7000S projects. After compilation, you can also use SOFs to cr

29、eate different types of files for configuring FLEX 6000, FLEX 8000 and FLEX 10K devices with Convert SRAM Object Files (File menu).vThe programming files can then be processed by the MAX+PLUS II Programmer and the MPU or APU hardware to produce working devices. Several other programming hardware man

30、ufacturers also provide programming support for Altera devices. v前往Simulation Mode vFunctionalvSimulates the behavior of flattened netlists extracted from the design files. You can use Tcl commands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec), although the Simulator uses only the sequence of