集成电路设计-05-反相器动静态特性

1、EIS-WUHAN UNIVERSITY1集成电路设计第五章第五章 CMOS反相器反相器EIS-WUHAN UNIVERSITY2Outlinen电路特性电路特性n反相器反相器nCMOS反相器电压传输特性反相器电压传输特性n噪声容限噪声容限n传输延迟传输延迟n驱动大电容负载驱动大电容负载q功耗及低功耗设计功耗及低功耗设计EIS-WUHAN UNIVERSITY35-1 特性n成本q复杂性和面积n完整性和稳定性q静态（稳态）特性n性能q动态（瞬态）特性n能量效率q能耗和功率EIS-WUHAN UNIVERSITY45-2 反相器（VinVoutCLVDDCMOS InverterPolysili

2、conInOutVDDGNDPMOS2l lMetal 1NMOSContactsN WellEIS-WUHAN UNIVERSITY5Two InvertersConnect in MetalShare power and groundVDDEIS-WUHAN UNIVERSITY6CMOS 反相器基本特点n输出输出q电源和电源和GNDGNDq噪声容限大噪声容限大n逻辑电平与尺寸无关，可以采用最小尺寸逻辑电平与尺寸无关，可以采用最小尺寸n稳态输出时，稳态输出时，VDDVDD或或GNDGND与输出之间总存在有限电阻的通路与输出之间总存在有限电阻的通路q低输出阻抗低输出阻抗q对噪声和干扰不敏感对

3、噪声和干扰不敏感n极高的输入阻抗（极高的输入阻抗（input resistanceinput resistance）n稳态下稳态下 V Vdddd 和和 GND GND 间无直流通路间无直流通路q无静态功耗无静态功耗n传输延迟（传输延迟（Propagation delayPropagation delay）q是负载电容和晶体管电阻的函数。是负载电容和晶体管电阻的函数。EIS-WUHAN UNIVERSITY7CMOS InverterFirst-Order DC AnalysisVOL = 0VOH = VDDVM = f(Rn, Rp)VDDVDDVin=VDDVin= 0VoutVoutR

4、nRpEIS-WUHAN UNIVERSITY8CMOS Inverter: Transient Response tpHL = f(Ron.CL)= 0.69 RonCLVoutVoutRnRpVDDVDDVin=VDDVin=0(a) Low-to-high(b) High-to-lowCLCLEIS-WUHAN UNIVERSITY95-3 Voltage Transfer CharacteristicnNMOS+PMOSn图解法EIS-WUHAN UNIVERSITY10I-V NMOSID (A)VDS (V)X 10-4VGS = 1.0VVGS = 1.5VVGS = 2.0VV

5、GS = 2.5VLinear dependenceNMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4VEIS-WUHAN UNIVERSITY11I-V Plot (PMOS)ID (A)VDS (V)X 10-4VGS = -1.0VVGS = -1.5VVGS = -2.0VVGS = -2.5VPMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4VAll polarities of all voltages an

6、d currents are reversedEIS-WUHAN UNIVERSITY12PMOS Load LinesVoutIDnVin = VDD+VGSpIDn = - IDpVout = VDD+VDSpVinVoutCLVDDEIS-WUHAN UNIVERSITY13PMOS Load LinesVDSpIDpVGSp=-2.5VGSp=-1VDSpIDnVin=0Vin=1.5VoutIDnVin=0Vin=1.5Vin = VDD+VGSpIDn = - IDpVout = VDD+VDSpEIS-WUHAN UNIVERSITY14CMOS Inverter Load Ch

7、aracteristics IDnVoutVin = 2.5Vin = 2Vin = 1.5Vin = 0Vin = 0.5Vin = 1NMOSVin = 0Vin = 0.5Vin = 1Vin = 1.5Vin = 2Vin = 2.5Vin = 1Vin = 1.5PMOSEIS-WUHAN UNIVERSITY15CMOS Inverter VTC VoutVin0.511.522.50.511.522.5NMOS resPMOS offNMOS satPMOS satNMOS offPMOS resNMOS satPMOS resNMOS resPMOS satEIS-WUHAN

8、UNIVERSITY16噪声容限logic 1logic 0unknownVDDVSSVHVLn反映了对噪声的敏反映了对噪声的敏感程度；感程度；n电路电路0 0，1 1电平允许电平允许的输入范围；的输入范围；n越大越好；越大越好；q高电平噪声容限高电平噪声容限q低电平噪声容限低电平噪声容限EIS-WUHAN UNIVERSITY17Logic level matchingnLevels at output of one gate must be sufficient to drive next gate.EIS-WUHAN UNIVERSITY18Transfer characteristic

9、snTransfer curve shows static input/output relationshiphold input voltage, measure output voltage.EIS-WUHAN UNIVERSITY19反相器噪声容限的三种求法n求法求法1q最低输出高电平、最高最低输出高电平、最高输出低电平；输出低电平；q找到对应的输入；找到对应的输入；q求差；求差；VNL=Voff VilVNH=Vih VonVolVol,maxVoh,minVohVonVihVoffVilEIS-WUHAN UNIVERSITY20n求法求法2q单位增益点（斜率为单位增益点（斜率为1，

10、-1）；）；q找到对应的输入；找到对应的输入；q求差；求差；VNL=Voff VilVNH=Vih VonVolVol,maxVoh,minVohVonVihVoffVilEIS-WUHAN UNIVERSITY21n求法求法3q工作中心点；工作中心点；nVin = VoutnVgs = Vdsq找到对应的输入；找到对应的输入；q求差；求差；EIS-WUHAN UNIVERSITY22Noise Margins Determining VIH and VILVinVoutVOH = VDDVMBy definition, VIH and VIL are where dVout/dVin = -

11、1 (= gain)VOL = GNDA piece-wise linear approximation of VTC NMH = VDD - VIH NML = VIL - GNDApproximating: VIH = VM - VM /g VIL = VM + (VDD - VM )/gSo high gain in the transition region is very desirableEIS-WUHAN UNIVERSITY23CMOS Inverter VTC from SimulationVin (V)Vout (V)0.25um, (W/L)p/(W/L)n = 3.4(

12、W/L)n = 1.5 (min size)VDD = 2.5VVM 1.25V, g = -27.5VIL = 1.2V, VIH = 1.3VNML = NMH = 1.2(actual values are VIL = 1.03V, VIH = 1.45VNML = 1.03V & NMH = 1.05V)Output resistance low-output = 2.4khigh-output = 3.3kEIS-WUHAN UNIVERSITY24VM与PMOS及NMOS的宽长比(W/L)p/(W/L)nVM (V)qIncreasing the width of the

13、PMOS moves VM towards VDDq Increasing the width of the NMOS moves VM toward GNDq决定因素：宽长比宽长比q近似为等效电阻之比。近似为等效电阻之比。.1工艺因子：工艺因子： k = Cox导电因子：导电因子： n = k（W/L）3.4Rn1/n (Vgs Vt)EIS-WUHAN UNIVERSITY25Gain DeterminatesVingainGain is a strong function of the slopes of the currents in the saturation region, fo

14、r Vin = VM (1+r)g - (VM-VTn-VDSATn/2)(ln - lp )Determined by technology parameters, especially channel length modulation (l). Only designer influence through supply voltage and VM (transistor sizing).EIS-WUHAN UNIVERSITY26Gain as a function of VDD00.000.0Vin (V)Vout (V)00.511.5

15、22.500.511.522.5Vin (V)Vout(V)Gain=-1n100mv时，时，VTC变差；变差；n过渡区增益接近过渡区增益接近-1n一般，为达到足够的增益，电源应大于热电势的两倍一般，为达到足够的增益，电源应大于热电势的两倍qVDDmin 2, 4 KT/qqKT/q室温下约为室温下约为26mvEIS-WUHAN UNIVERSITY27Simulated VTC 00.511.522.500.511.522.5Vin (V)Vout(V)EIS-WUHAN UNIVERSITY28Impact of Process Variations00.511.522.500.511.5

16、22.5Vin (V)Vout(V)Good PMOSBad NMOSGood NMOSBad PMOSNominalEIS-WUHAN UNIVERSITY295-4 传输延迟（Propagation Delay）EIS-WUHAN UNIVERSITY30DelaynAssume ideal input (step), RC load.EIS-WUHAN UNIVERSITY31tpHL = f(Ron.CL)= 0.69 RonCLVoutVoutRnRpVDDVDD(a) Low-to-high(b) High-to-lowCLCLn上升时间（rise time）, pullup on

17、;n下降时间（fall time）, pullup off.EIS-WUHAN UNIVERSITY32Current through transistornTransistor starts in saturation region, then moves to linear region.nVout增大增大q充电电流减小。充电电流减小。q Vds 减小。减小。EIS-WUHAN UNIVERSITY33Resistive approximation可使用积分求解可使用积分求解等效电阻平均值等效电阻平均值VGS VTRonSDEIS-WUHAN UNIVERSITY34Req求求VDD/2，

18、VDD区间的电阻平均值区间的电阻平均值EIS-WUHAN UNIVERSITY35Gate delaynDelay: 传输延迟nVDD 50% VDD n50% VDD VDDnTransition time: 转换时间qtime required for gates output to reach 10% (logic 0) or 90% (logic 1) of final value.n10% 90%n90% 10%EIS-WUHAN UNIVERSITY36Inverter delay circuitnLoad is resistor + capacitor, driver is re

19、sistor.EIS-WUHAN UNIVERSITY37Inverter delay with t modelnt model: qgate delay based on RC time constant t.nVout(t) = VDD exp-t/(Rn+RL)CLn90% (logic 1) 10% (logic 0) qtf = 2.2 R CLn100% (logic 1) 50%qtD= 0.69 R CLnFor pullup time, use pullup resistance.EIS-WUHAN UNIVERSITY38t model inverter delay n0.

20、5 micron process: qRn = 3.9 kqCL= 0.68 fFn延迟时间qtd = 0.69 x 3.9 x 0.68E-15 = 1.8 ps.n上升延迟qtf = 2.2 x 3.9 x 0.68E-15 = 5.8 ps.EIS-WUHAN UNIVERSITY39Quality of RC approximationEIS-WUHAN UNIVERSITY40VDDVoutVin = VDDRonCLtpHL = f(Ron.CL)= 0.69 RonCLtVoutVDDRonCL10.5ln(0.5)0.36EIS-WUHAN UNIVERSITY4100.511

21、.522.5x 10-10-0.500.511.522.53t (sec)Vout(V)传播延迟50%平均延迟时间tp = 0.69 CL (Reqn+Reqp)/2tpLHtpHLVOUT = 0.5VDD时时EIS-WUHAN UNIVERSITY42nRn1/n1/n n ( (Vgs Vt)qRn1/n1/n nn导电因子qn n = k（W/L）qk = n Coxn CoxqCgCg = CoxCox *(W*L）EIS-WUHAN UNIVERSITY43Delay as a function of VDD0.81.822.22.411.522.533.544

22、.555.5VDD(V)tp(normalized)EIS-WUHAN UNIVERSITY44n等效电阻与等效电阻与W/LW/L成反比；成反比；n当当V VDDDDVt+VVt+VDDDD/2/2时，等效电阻与电源无关；时，等效电阻与电源无关；n当当V VDDDD=Vt zero delayCLtp = k RWCLRWRWWunit = 1k is a constant, equal to 0.69EIS-WUHAN UNIVERSITY51输出端电容构成输出端电容构成nCout = CFET + CLntf = 2.2 Rn ( CFET + CL )ntr = 2.2 Rp ( CFE

23、T + CL )nCFET 由几何图形决定由几何图形决定EIS-WUHAN UNIVERSITY52Inverter with LoadLoadDelayCintCLDelay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= Delay (Internal) + Delay (Load)CN = CunitCP = 2Cunit2WWEIS-WUHAN UNIVERSITY53Delay Formula/1/10intftCCCkRtCCRDelaypintLWpLintWCint = Cgin with 1f = CL/

24、Cgin - effective fanoutR = Runit/W ; Cint =WCunittp0 = 0.69RunitCunitEIS-WUHAN UNIVERSITY54Apply to Inverter ChainCLInOut12Ntp = tp1 + tp2 + + tpNjginjginunitunitpjCCCRt,1,1LNginNijginjginpNjjppCCCCttt1,1,1,01, ,1EIS-WUHAN UNIVERSITY55Optimal Tapering for Given NDelay equation has N - 1 unknowns, Cg

25、in,2 Cgin,NMinimize the delay, find N - 1 partial derivativesResult: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1Size of each stage is the geometric mean of two neighbors- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay1,1,jginjginjginCCCEIS-WUHAN UNIVERSITY56延迟时间及级数优化1 ,/gin

26、LNCCFfWhen each stage is sized by f and has same eff. fanout f:NFf /10NppFNttMinimum path delayEffective fanout of each stage:EIS-WUHAN UNIVERSITY57ExampleCL= 8 C1InOutC1283fCL/C1 has to be evenly distributed across N = 3 stages:EIS-WUHAN UNIVERSITY58级数优化For a given load, CL and given input capacita

27、nce CinFind optimal sizing ffffFtFNttpNpplnlnln1/0/100ln1lnln20fffFtftppfFNCfCFCinNinLlnln with EIS-WUHAN UNIVERSITY59级数的近似收敛解收敛解：For = 0, f = e, N = lnFff1expCint = Cgin此时，忽略自载。此时，忽略自载。f = e =2.71828,N = lnFEIS-WUHAN UNIVERSITY60Optimum Effective Fanout fOptimum f for given process defined by ff1ex

28、pfopt = 3.6for =1EIS-WUHAN UNIVERSITY61Buffer Design111186464646442.881622.6Nftp164652818341542.815.3EIS-WUHAN UNIVERSITY625-6 功耗（Power Dissipation） Lead microprocessors power continues to increaseP6Pentium 486386286808680858080800840040.1110100197119741978198519922000YearPower (Watts)EIS-WUHAN UNIV

29、ERSITY63Chip Power Density40048008808080858086286386486PentiumP611010010001000019701980199020002010YearPower Density (W/cm2)Hot PlateNuclearReactorRocketNozzleSunsSurfacechips might become hotSource: Borkar, De Intel EIS-WUHAN UNIVERSITY64Chip Power Density DistributionnPower density is not uniforml

30、y distributed across the chipnSilicon is not a good heat conductornMax junction temperature is determined by hot-spotsqImpact on packaging, coolingPower MapOn-Die TemperatureEIS-WUHAN UNIVERSITY65Power DissipationSource: Borkar, De Intel n来源：来源：q动态功耗（动态功耗（Dynamic Power Consumption）nCharging and Disc

31、harging Capacitorsq短路电流（短路电流（ Short Circuit Currents ）nCircuit Path between Supply Rails during Switchingq漏电流（漏电流（Leakage）nLeaking diodes and transistorsEIS-WUHAN UNIVERSITY66Power consumption circuitnInput is square wave.EIS-WUHAN UNIVERSITY67驱动电路ni(t)=dQ/dt ，i=c*dV/dtq电压不能突变，栅电压的变电压不能突变，栅电压的变化有延迟时

32、间。化有延迟时间。nQ=CVqC大，意味着延迟时间加长大，意味着延迟时间加长n影响影响C的因素？的因素？P=V（C*dV/dt）=d （ 0.5CV2 ） /dtE= 0.5C V2输入从0到VDD时，E= 0.5C VDD2每次开关消耗能量。EIS-WUHAN UNIVERSITY68动态功耗动态功耗VinVoutCLVddnA single cycle qE = CL(VDD - VSS)2 .nClock frequency f = 1/t.nEnergyq E = CL(VDD - VSS)2.nPower q E * f = f CL(VDD - VSS)2.n影响因素q f qCL

33、qVDD 其中负载消耗其中负载消耗1/2。EIS-WUHAN UNIVERSITY69Energy/transition = CL * VDD2 * P01Pdyn = （Energy/transition） * f = CL * VDD2 * P01 * fPdyn = CEFF * VDD2 * f where CEFF = P01 CL f01Data dependent - a function of switching activity!EIS-WUHAN UNIVERSITY70nConsider a 0.25 micron chip, 500 MHz clock, average

34、 load cap of 15fF/gate (fanout of 4), 2.5V supply. qDynamic Power consumption per gate is ?q46.875uw ? nWith 1 million gates (assuming each transitions every clock) qDynamic Power of entire chip = ?.n46.875w ?EIS-WUHAN UNIVERSITY71Lowering Dynamic PowerPdyn = CL VDD2 P01 fCapacitance:Function of fan

35、-out, wire length, transistor sizesSupply Voltage:Has been dropping with successive generationsClock frequency:IncreasingActivity factor:How often, on average, do wires switch?EIS-WUHAN UNIVERSITY72Speed-power productnPower-delay product (PDP ）nSP = P/f = CV2EIS-WUHAN UNIVERSITY73短路电流（短路电流（Short Cir

36、cuit Current）IV DD (mA)5Vin (V)5.04.03.02.01.00.0VinVoutCLVddEIS-WUHAN UNIVERSITY74nDuration and slope of the input signal, tscnIpeak determined by qthe saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc.qstrong function of the

37、ratio between input and output slopesna function of CLEsc/transition = tsc VDD Ipeak P01Psc = tsc VDD Ipeak f01EIS-WUHAN UNIVERSITY75Ipeak as a Function of CLIpeak (A)time (sec)x 10-10 x 10-4CL = 20 fFCL = 100 fFCL = 500 fFEIS-WUHAN UNIVERSITY76Impact of CL on PscVinVoutCLIsc 0VinVoutCLIsc ImaxLarge capacitive loadSmall capacitive loadEIS-WUHAN UNIVERSITY77Psc as a Function of Rise/Fall TimesP normalizedtsin / tsoutVDD= 3.3 VVDD = 2.5 VVDD = 1.5VWhen load capacitance is small (tsin/tsout 2 for VDD 2V) the power is dominated by PscW/Lp = 1.125 mm/0.25 mmW/Ln = 0.375 mm/0.25 mmCL