verilog并串转换

1、实用文档题目要求：实现8位的并行数据转换为串行的数据。题目分析：并行转串行，只要把每个输入按从高到低的顺序输出即可。即每个时钟脉冲输出一个数据。但是下面的代码有一个的问题，不能解决在8为数据串行 输出的过程当中如果又有一个并行的输入数据输入，没有做到缓冲处理。也许这个缓冲处理可以在调用此模块时在外部实现吧。功能代码：module para_to_serial_8bit(para_i n, clock,reset,ser_out);in put 7:0 para_ in;in put reset,clock;output ser_out;reg ser_out;reg 7:0 data;alwa

2、ys(posedge clock or n egedge reset) beg inif(reset) begi nser_out = 1b0;data = para_i n;endelse begi ndata = data6:0,data7;ser_out = data7;endenden dmodule测试代码：module test_para_to_ser;reg 7:0 para_i n;reg clock,reset;wire out;para_to_serial_8bitf1(.para_ in( para_i n),.clock(clock),.reset(reset),.se

3、r_out(out);in itial$mo nitor($time,in_8bit=%b,reset= %b,ser_out= %b,data=%b,para_ in, reset,out,f1.data);in itial begi nclock = 1b0;reset = 1b0;#3 reset = 1b1;#300 $stop;endin itial实用文档para_in = 8b1010_0100;always#5clock = clock;en dmodule测试结果:测试波形如下:作业二题目要求：实现8位的串行数据转换为并行的数据题目分析：8位串行数据转换为并行数据，需要一个模

4、为8的计数器，当计到8个时钟脉冲时，把之前的8个数据全部输出，然后从新接收。功能模块代码：模8计数器：module coun ter_mod_8(clock,reset,Q);in put clock; /posedge effectivein put reset; / n egedge effective实用文档output 2:0 Q;reg 2:0 Q;always(posedge clock or n egedge reset) begi nif(reset)Q = 3d0;elseQ = Q + 1;enden dmodule串转并模块：module ser_to_par_8bit(

5、ser_ in, clk,rst,out);in put ser_ in, clk,rst;output 7:0 out;wire 7:0 out;reg 7:0 par_out;wire 2:0 count;coun ter_mod_8 f1(.clock(clk),.reset(rst),.Q(co un t);always(posedge clk or n egedge rst) beg inif(rst)par_out = 8b0000_0000;else begi npar_out = par_out6:0,ser_ in;endendassign out = (count = 7)

6、? par_out : 8b0000_0000; en dmodule测试模块代码：module test_ser_par;reg 7:0 data;wire data_i n;reg clock, reset;wire 7:0 out;in itial begi nclock = 1b0;实用文档reset = 1bO;#3 reset = 1b1;data = 8b1001_1101;#300 $stop;endalways#5clock = clock; always(posedge clock)data =data6:0,data7; assig n data_ in = data7;

7、ser_to_par_8bit a(.ser_ in( data_ in ),.clk(clock),.rst(reset),.out(out);in itial%b,data= %b,data_i n= %b,out= %b,reset,data,data_i n,out);测试结果:测试波形:$mo nitor($time,reset=en dmodule实用文档作业三题目：可变模计数器，当控制信号为1时，模值为16,当控制信号为0是模值 为32。功能模块代码：/ contr = 1 mod =16; contr =0 mod =32module coun t_mod_chg(clk,re

8、set,c on tr,Q);in put clk,reset,c ontr;output 4:0 Q;实用文档reg 4:0 Q;wire 4:0 last;assign last =(contr ? 5b01111:5b11111);always(posedge clk or n egedge reset) beg inif(reset | Q = last)Q = 5b00000;elseQ = Q + 1;enden dmodule测试模块代码：module test_co un t_mod_chg;reg clock,reset;reg con trol;wire 4:0 out;c

9、oun t_mod_chg coun ter1(.clk(clock),.reset(reset),.c ontr(con trol),.Q(out); in itial$mon itor($time,reset= %b,c on trol= %b,out= %b,reset,c on trol,out);in itial beg inclock = 1b0;forever #5 clock = clock;endin itial begi n reset = 1b0;#5reset = 1b1; endin itial begi ncon trol = 1;#200 control = 0;enden dmodule测试结果:实用文档仿真波形如下实用文档f Wae:Messages deck0L_TT TLTLTTjirlrLn rLnrrkTln_reset1controlQD outooinotaciloa jckxniitookiKuiiboiio!bciii：roSDionniKObiioiMjiiDtomitaotaoiM10FT阴帼-MessagesJM1x rn jn_rTr1L r1 -ruL rJreset1Jcontrol0D-Jout1100 o.lotouii