EDA程序改错题

1、程序改错题1. 已知 sei 为 STD_L0GIC_VECT0R(1 DOWNTO 0)类型的信号，而 a b、c、d、 q 均为 STD_LOGIC 类型的信号，请判断下面给出的 CASE 语句程序片段：=>q<=a；=>q<=b；=>q<=c； =>q<=d；CASE sei IS WHE“N 00” WHE“N 01 ” WHE“N 10” WHE“N 11 ”END CASE； 答案：CASE语句缺“ WHEN OTHERS语句。2. 已知 datan1, datan2为 STD_LOGIC_VECTOR(15 DOWNTO 0) 类型

2、的输入 端口，data_out为 STD_LOGIC_VECTOR(15 DOWNTO 0)类型的输出端口， add_sub为STD_LOGIC类型的输入端口，请判断下面给出的程序片段：LIBRARY IEEE ；USE ；ENTITY add ISPORT(data_in1 , data_in2： IN INTEGER；data_out： OUT INTEGER)；END add；ARCHTECTURE add_arch OF add ISCONSTANT a:INTEGER<=2；BEGIN data_out<=( data_in1+ data_in2) * a；END add

3、sub_arch；答案：常量声明时赋初值的“ <=”符号应改用“ := ”符号。3. 已知Q为STD_LOGIC类型的输出端口，请判断下面的程序片段：ARCHITECTURE test_arch OF test ISBEGINSIGNAL B： STD_LOGIC；Q<= B ；END test_arch答案：信号 SIGNAL 的声明语句应该放在 BEGIN 语句之前。4. 已知A和Q均为BIT类型的信号，请判断下面的程序片段：ARCHITECTURE archtest OF test ISBEGINCASE A ISWHEN0'=>Q<=；1'WHE

4、N1'=>Q<=；0'END CASE；END archtest；答案：CASE语句应该存在于进程 PROCESS内。B <= 'x'请判断下面的程序片断：1 已知 A 和 Q 均为 BIT 类型的信号，ARCHITECTURE test OF test ISBEGINCASE A ISWHEN '0' => Q <= '1'WHEN '1' => Q <= '0'END CASEEND test ；参考答案】： CASE 语句应该存在于进程PROCESS

5、内。2 已知 start 为 STD_LOGIC 类型的信号，sum 是 INTEGER 类型的信号，请判断下面的程序片断：PROCESS (start)BEGINFOR i IN 1 TO 9 LOOPsum := sum + i ；END LOOPEND PROCES；S参考答案】： sum 是信号，其赋值符号应该由“ :=”改为“ <=”。3 已知 Q 为 STD_LOGIC 类型的输出端口，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINSIGNAL B ：STD_LOGICQ <= B ；END test ；参考答案】： 信号 SI

6、GNAL 的申明语句应该放在 BEGIN 语句之前。4 已知 A 和 B 均为 STD_LOGIC 类型的信号，请判断下面的语句：A <= '0'【参考答案】：不定态符号应该由小写的 X'改为大写的 X '。5 已知 A 为 INTEGER 类型的信号， B 为 STD_LOGIC 类型的信号，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINB <= A ；END test ；【参考答案】：A和B的数据类型不一致，不能相互赋值。6.已知sei 是STD_LOGIC_VECTOR(1 DOWNTO型信号，而 a、

7、b、c、d、q均为STD_LOGI类型信号，请判断下面给出的CAS语句:CASE sei ISWHEN“00”=> q<=WHEN“01”=> q<=WHEN“10”=> q<=WHEN“11”=> q<=END CASE；CASE语句缺“ WHEN OTHERSI句。【参考答案】：四、判断下面程序中是否有错误，若有错误请改正；1、SIGNAL A,EN:STD_LOGIC;PROCESS(A,EN)VARIABLE B:STD_LOGIC;BEGINIF EN=1' THENB<=A;END ;END PROCESS;2、RCHI

8、TECTURE ONE OF SAMPLE IS VARIABLE A， B， C： INTEGER； BEGINC<=A+B；END ;五、判断下列程序是否有错误，如有则指出错误所在(10分)程序：LIBRARY IEEE;USE zyt12 IS PORT(R,EN,CP: IN bit;Q: BUFFER STD_LOGIC_VECTOR(0 DOWNTO 3);CO: OUT STD_LOGIC);END zyt;ARCHITECTURE c10 OF zyt12BEGINCO<='1' WHEN(EN='1' AND Q="101

9、1") ELSE'0'PROCESS(R,CP)BEGINIF R='1' THENQ<="0000"ELSIF (CP'EVENT AND CP<='1') THEN IF EN='0' THENQ<=Q;ELSIF Q="1011" THENQ<= 0000' ;ELSEQ:=Q+1;END IF;END PROCESS;END one;仔细阅读下列程序，回答问题LIBRARY IEEE;USEENTITY LED7SEG IS- 2PO

10、RT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); CLK : IN STD_LOGIC;LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END LED7SEG;ARCHITECTURE one OF LED7SEG IS SIGNAL TMP : STD_LOGIC;BEGINSYNC : PROCESS(CLK, A)BEGINIF CLK'EVENT AND CLK = '1' THEN TMP <= A;END IF;END PROCESS;OUTLED : PROCESS(TMP)BEGI

11、NCASE TMP ISWHEN "0000" => LED7S <= "0111111"WHEN "0001" => LED7S <= "0000110"WHEN "0010" => LED7S <= "1011011"WHEN "0011" => LED7S <= "1001111"- 7- 9- 11- 12- 13- 14- 15- 18- 19- 20- 21- 22- 23-

12、1- 3- 4- 5- 6- 8- 10- 16- 17- 24- 25- 26- 27- 28- 29- 30- 31- 32WHEN "0100" => LED7S <= "1100110"WHEN "0101" => LED7S <= "1101101"WHEN "0110" => LED7S <= "1111101"WHEN "0111" => LED7S <= "0000111"

13、WHEN "1000" => LED7S <= "1111111"WHEN "1001" => LED7S <= "1101111"END CASE;END PROCESS;END one;1. 在程序中存在两处错误，试指出，并说明理由： 第 14 行 TMP 附值错误第 29 与 30 行之间，缺少 WHEN OTHERS 语句2. 修改相应行的程序：错误 1 行号： 9 程序改为：TMP : STD_LOGIC_VECTOR(3 DOWNTO 0);错误 2 行号： 29 程序改为： 该

14、语句后添加 WHEN OTHERS => LED7S <= "00000001、LIBRARY IEEE;USEUSEENTITY CNT4B ISPORT (CLK，RST，ENA: IN STD_LOGIC;OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT4B;ARCHITECTURE behav OF CNT4B ISSIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK, RST, ENA)IF RST = &#

15、39;1' THEN CQI <= '0000'ELSIF CLK'EVENT AND CLK = '1' THENIF ENA = "1" THEN CQI <= CQI + 1;"0000"'1'ELSE CQI <= "0000"BEGINEND IF;END IF；OUTY <= CQI ;END P ROCESS;COUT<=CQI(0) and CQI(1) and CQI (2) AND CQI (3);END behav;2、

16、LIBRARY IEEE;USEUSEUSE CLK_6D ISP ORT (CLK,RST: IN STD_LOGIC;CLK_OUT: OUT STD_LOGIC);END CLK_6D;ARCHITECTURE ONE OF CLK_6D ISVARIABLE TEMP:STD_LOGI(SIGNALP ROCESS(CLK)VARIABLE CNT6D: INTEGER RANGE 0 TO 3;CONSTANT SIGN: INTEGER:=2;BEGIN'1' , 'O'IF (RST =“ 1”)THEN TEMP <= “0” ;ELSIF

17、 CLK'EVENT AND CLK='1' THEN (CLK'EVENT AND CLK='1')IF (CNT6D = SIGN) THENCNT6D := 0;TEMP <= NOT TEMP;ELSE CNT6D := CNT6D+1;END IF;END IF;END P ROCESS;CLK_OUT <= TEMP;END ONE;3、library ieee;use en coder isport(b；_ in std_logic(7downto 0); b:in std_logic_vector(7downto 0)

18、y_out std_logic(2 dow nto 0);y:out std_logic_vector(2 dow nto 0)end en coder;architecture one of encoder is begin process (b)when others => null;end case;end process;end one;4、LIBRARY IEEE;USEENTITY counter ISPORT ( reset: IN STD_LOGIC; clock: IN STD_LOGIC;； 多一个“； ”num: buffer integer range 0 to

19、3 );END;ARCHITECTURE behav OF jishu IS jishu 改为 counterBeginProcess(reset,clock)BeginIf reset= '1' then num<=0;Elsif rising_edge(clock) thenIf num=3 the nnum<=0;elsenum<二nu m+1;少 end if;end if;end p rocess;end;5、LIBRARY IEEE;USEUSE ;ENTITY LX3 2 ISP ORT(CLK,CLR,OE:IN BIT;D:IN STD_LO

20、GIC_VECTOR(7 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END LX3_2;ARCHITECTURE struc OF LX3_2 ISVARIABLE Q_TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNALBEGINP ROCESS(CLR)P ROCESS(CLK)"00000000"BEGINIF CLR='0' THEN Q_TE MP <='00000000'ELSIF CLK='1' THENQ_TE MP v=D;ELS