EDA电子设计自动化实验

1、library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ctrl is port(clr,clk,sp:in std_logic; en:out std_logic);end ctrl;architecture behave of ctrl is type states is (s0,s1,s2,s3); signal current_state,next_state:states; begin com:process(sp,current_state) begin case current

2、_state iswhen s0=>en<='0'if sp='1' then next_state<=s1;else next_state<=s0;end if;when s1=>en<='1'if sp='1' then next_state<=s1;else next_state<=s2;end if;when s2=>en<='1'if sp='1' then next_state<=s3;else next_state<

3、;=s2;end if;when s3=>en<='0'if sp='1' then next_state<=s3;else next_state<=s0;end if; end case; end process;synch:process(clk) begin if clr='1' then current_state<=s0; elsif clk'event and clk='1' thencurrent_state<=next_state; end if;end process;

4、end behave;library ieee;use ieee.std_logic_1164.all;entity cb10 isport(clk: in std_logic; co: buffer std_logic);end cb10;architecture art of cb10 issignal counter:integer range 0 to 49999;begin process(clk) begin if (clk='1' and clk'event) then if counter=49999 thencounter<=0;co<=

5、not co; elsecounter<=counter+1; end if; end if; end process;end art;library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cdu10 isport(clk,clr,en: in std_logic;cn: out std_logic;count10: out std_logic_vector(3 downto 0);end cdu10;architecture art of cdu10 issignal temp:

6、std_logic_vector(3 downto 0);beginprocess(clk,clr)beginif clr='1' then temp<="0000"cn<='0' elsif (clk'event and clk='1') then if en='1' then if temp>="1001" then temp<="0000"cn<='1' else temp<=temp+1; cn<=

7、'0' end if; end if; end if; count10<=temp;end process;end art;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cdu6 isport(clk,clr,en: in std_logic;cn: out std_logic; count6: out std_logic_vector(3 downto 0);end cdu6;architecture art of cdu6 issignal temp:st

8、d_logic_vector(3 downto 0);begin process(clk,clr)beginif clr='1' then temp<="0000"cn<='0' elsif (clk'event and clk='1') thenif en='1' then if temp="0110" then temp<="0000"cn<='1' else temp<=temp+1;cn<='0&

9、#39; end if; end if; end if; count6<=temp; end process; end art;library ieee;use ieee.std_logic_1164.all;entity count is port(clk:in std_logic; clr:in std_logic;en:in std_logic;S_10ms:out std_logic_vector(3 downto 0);S_100ms:out std_logic_vector(3 downto 0);S_1s:out std_logic_vector(3 downto 0);S

10、_10s:out std_logic_vector(3 downto 0);M_1min:out std_logic_vector(3 downto 0);M_10min:out std_logic_vector(3 downto 0);end count;architecture art of count is component cdu10 port(clk,clr,en: in std_logic;cn: out std_logic;count10: out std_logic_vector(3 downto 0); end component cdu10; component cdu6

11、 port(clk,clr,en: in std_logic;cn: out std_logic; count6: out std_logic_vector(3 downto 0); end component cdu6;signal A,B,C,D,E,F:std_logic;begin U1:cdu10 port map (clk,clr,en,A,S_10ms);U2:cdu10 port map (A,clr,en,B,S_100ms);U3:cdu10 port map (B,clr,en,C,S_1s);U4:cdu6 port map (C,clr,en,D,S_10s);U5:

12、cdu10 port map (D,clr,en,E,M_1min);U6:cdu10 port map (E,clr,en,F,M_10min);end art;library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned; entity bcd7 is port(bcd:in std_logic_vector(3 downto 0); led:out std_logic_vector(6 downto 0); end bcd7 ; architecture art of bcd7 is begin led<

13、= "0111111" when bcd="0000"else "0000110" when bcd="0001"else "1011011" when bcd="0010"else "1001111" when bcd="0011"else "1100110" when bcd="0100"else "1101101" when bcd="0101"els

14、e "1111101" when bcd="0110"else"0000111" when bcd="0111"else"1111111" when bcd="1000"else"1101111" when bcd="1001"else"0000000"end art; library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_UNSIGNED.all;e

15、ntity mulx is port(clk:in std_logic; clr:in std_logic;en:in std_logic;S_10ms:in std_logic_vector(3 downto 0);S_100ms:in std_logic_vector(3 downto 0);S_1s:in std_logic_vector(3 downto 0);S_10s:in std_logic_vector(3 downto 0);M_1min:in std_logic_vector(3 downto 0);M_10min:in std_logic_vector(3 downto

16、0);outbcd:out std_logic_vector(3 downto 0);seg:out std_logic_vector(2 downto 0);end mulx;architecture art of mulx issignal count:std_logic_vector(2 downto 0);beginprocess(clk)beginif (clr='1') then count<="111"elsif (clk='1'and clk'event) thenif en='1' thenif

17、 count="101" thencount<="000" else count<=count+1;end if;end if;end if;end process;process(clk) begin if clk'event and clk='1'thencase count iswhen "000"=>outbcd<=S_10ms; seg<="000"when "001"=>outbcd<=S_100ms; seg<

18、="001"when "010"=>outbcd<=S_1s; seg<="010"when "011"=>outbcd<=S_10s; seg<="011"when "100"=>outbcd<=M_1min; seg<="100"when "101"=>outbcd<=M_10min; seg<="101"when others=>nu

19、ll;end case;end if;end process;end art;library ieee;use ieee.std_logic_1164.all;entity stopwatch is port (sp:in std_logic ; clr:in std_logic; clk:in std_logic; led:out std_logic_vector(6 downto 0); seg:out std_logic_vector(2 downto 0);end stopwatch;architecture art of stopwatch is component ctrl por

20、t(clr:in std_logic ; clk:in std_logic ;sp:in std_logic ;en:out std_logic ); end component; component cb10 port(clk:in std_logic; co:out std_logic); end component; component count port (clk:in std_logic; clr:in std_logic; en:in std_logic; S_10ms:out std_logic_vector(3 downto 0); S_100ms:out std_logic

21、_vector(3 downto 0); S_1s:out std_logic_vector(3 downto 0); S_10s:out std_logic_vector(3 downto 0); M_1min:out std_logic_vector(3 downto 0); M_10min:out std_logic_vector(3 downto 0); end component; component bcd7 port(bcd:in std_logic_vector(3 downto 0); led:out std_logic_vector(6 downto 0); end component; component mulx port (clr:in std_logic; clk:in std_logic; en:in std_logic; S_10ms:in std_logic_vector(3 downto 0);S_100ms:in std_logic_vector(3