caputer生成网表报错原因解析#精选

1、(1) Warning "No_connect"#1 Warning ALG0047 "No_connect" property on Pin "P1.8" ignored forP1: SCHEMATIC1, 13)URAT (7.90, 1.20). Connecting pin to net "N16811229".&H)K-hwM$k3D3pd-T$W7heALG0047这个警告基本可以忽略；造成这个问题的原因是，设计之 初先对器件相关的管脚上加上'X'(也就是NC符号)，更新设计的

2、过 程又对管脚做了连接处理；但是后面的连接处理没有去掉管脚的NC属性，不信的话把那个管脚上的net删掉看看。RG9f 解决办法很简单，对这些管脚再做一次NC(2) Warning Part Name#5 Warning ALG0016 Part Name "CAP PN_C100UP-6.3V-SMT- S_100UF/6.3V" is renamed to "CAP PN_C100UP-6.3V-SMT- S_100UF/"这个警告不可避免，allegro对相关的属性名称进行合并，超过一定数量的字符就截掉；在命名规范的前提下就不考虑这个警告了。无法根治

3、 这个 #2 Warning ALG0016 Part Name "?j#w?rm之类的错误在于你建立元件原理图的时候你的原件Value值太长了超过32个字符,从而使系统在进行命名规范的时候溢出，而出错,很 简单的，只写关键元件名，比如A2541P10_HDR2X5-100MIL_2X5 HEADER" is renamed to "A2541P10_HDR2X5-100MIL_2X5 HEAD1误 只需要把2X5 HEADE哽改为A2541P10,去除中间的空格即可 二Allegro对一些字符例如"空格","小数点"等等很

4、在意，可以参阅 相关文档的描述.(3) Error Illegal character "Dot(.)" found in "PCB Footprint"1 / 9word.#1 Error ALG0081 Illegal character "Dot(.)" found in "PCB Footprint" property for component instance C255: PG16_AC97, PG16_AC97 (226.06, 132.08).封装命名不能包含“.”(4) Error Illegal

5、 character "Forward Slash(/)" found in "PCB Footprint" property# 1 Error ALG0081 Illegal character "Forward Slash(/)” found in "PCB Footprint" property for component instance C255: PG16_AC97, PG16_AC97 (226.06, 132.08).# 2 Error ALG0081 Illegal character "Forw

6、ard Slash(/)” found in "PCB Footprint" property for component instance D3: PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp (93.98, 33.02).# 3 Error ALG0081 Illegal character "Forward Slash(/)" found in "PCB Footprint" property for componen

7、t instance C245: PG16_AC97, PG16_AC97 (205.74, 35.56). 封装命名不能包含“ /”(5)比较隐藏的排除法Loading. E:FPGASCHallegroestchip.dat#34 WARNING(SPCODD-34Expected '' character on line 5308.Check the name and value syntax for invalid characters in the primitive definition before the line number.ERROR(SPCODD-47)

8、: File ./allegro/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.2 / 9word.#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID.

9、The design may not have been saved correctly. Save the schematic and rerun packaging.#187 Error ALG0036 Unable to read logical netlist data.Exiting. "D:CadenceSPB_16.2toolscapturepstswp.exe"- pst -d "E:FPGASCHmotherboard.dsn" -n "E:FPGASCHallegro" -c "D:CadenceSPB_

10、16.2toolscaptureallegro.cfg" -v 3 -j "PCB Footprint"*Done*掌握排错方法，查找文件pstchip.dat ,第on line 5308 看看错误，便可以解决(6)封装命名中不能包含“小数点”、“ /”、“空格”，把空格 换成下划线或删除，可以解决* Netlisting the design*Design Name:E:FPGASCHbasicboard.dsnNetlist Directory:E:FPGASCHallegroConfiguration File:D:CadenceSPB_16.2tools

11、captureallegro.cfgSpawning. "D:CadenceSPB_16.2toolscapturepstswp.exe-pst -d "E:FPGASCHbasicboard.dsn" -n3 / 9word."E:FPGASCHallegro" -c "D:CadenceSPB_16,2toolscaptureallegro.cfg" -v 3 -j "PCB Footprint"(1) Error ALG0081 Illegal character "White space

12、" found in "PCB Footprint" property for component instance MG2: Basic, PG06_Stepmotor (180.34, 83.82).(2) Error ALG0081 Illegal character "White space" found in "PCB Footprint" property for component instance ISO1: Basic, PG05_DC Motor (134.62, 40.64).(3) Info: PCB

13、 Editor does not support Dots(.), Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).(4) Aborting Netlisting. Please correct the above errors and retry.Exiting. "D:CadenceSPB_16.2toolscapturepstswp.exe"- ps

14、t -d "E:FPGASCHbasicboard.dsn" -n "E:FPGASCHallegro" -c "D:CadenceSPB_16.2toolscaptureallegro.cfg" -v 3 -j "PCB Footprint"*Done *封装命名中不能包含“小数点”、 划线或删除，可以解决/"、“空格”，把空格换成下(7) Warning#11 Warning ALG0051 Pin "GND" is renamed to "GND#A6" af

15、ter substituting illegal characters in Package XC3S1400A- 4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).4 / 9word.#12 Warning ALG0051 Pin "GND" is renamed to "GND#A11" after substituting illegal characters in Package XC3S1400A- 4FG676-C_0FF , U1A: SCHEMATIC1, PG01_

16、FPGACONFIG (2.40, 3.10).#13 Warning ALG0051 Pin "GND" is renamed to "GND#A1" after substituting illegal characters in Package XC3S1400A- 4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).#14 Warning ALG0051 Pin "GND" is renamed to "GND#W8" after sub

17、stituting illegal characters in Package XC3S1400A- 4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).这条警告信息，在命名规范的前提下就不考虑这个警告了。 无法根治，除非去除检测(8)# 60 Warning ALG0016 Part Name"COM_17 2_SIP17X2_COM_1>72" is renamed to "COM_172_SIP17X2_COM_172".# 61 Warning ALG0060 No pi

18、ns are present in J53. Ignoring this component in netlist.# 62 Warning ALG0016 Part Name “1X3P,MALE,DIP_2.0_SIP3_1X3P_2.54MM" is renamed to “1X3P,MALE,DIP_2.0_SIP3_1X3P_2.5”.器件管脚不存在，有的器件做了但没放管脚，正常(9) error: Same Pin Number connected to more than one net.5 / 9word.请检查这个器件的位号是否有重复。一般是重复了才会出现这种 情况

19、。Checking Pins and Pin ConnectionsERROR: DRC0031 Same Pin Number connected to more than one net. LED&Switch&7- Segment Disp/U17/3 Nets: '3V3' and '485_RE/DE'.PG01_LED&Switch&7-Segment Disp,PG01_LED&Switch&7SegmentDisp (101.85, 73.66)上面的问题是器件位号重复(10)WARNING: DR

20、C0008 Two nets in same schematic have the same name, but there is no off-page connector这个问题是信号同名，到没有用 OFF-PAGE1接起来 生成网表会自 动重新命名一个名字(11) 1. Unable to open c:CadencePSD_14.2toolscaptureallegro.cfg for reading.Please correct the above error(s) to proceed错误解释：allegro.cfg 文件找不到或allegro.cfg文件不能打开，这个问题的根源是

21、，有可能每台电脑上安装 Allegro的的位置不一样， allegro.cfg文件找不到是理所当然的。处理办法：点生成 netlist ,点 setup ,修改路径为 captureallegro.cfg 所在 路径，把allegro.cfg文件的位置选择你现在安装目录的文件位置。(12) Spawning. "C:CadencePSD_15.1toolscapturepstswp.exe" -pst -d "F:gchtCC2430Projectsmysch.dsn" -n6 / 9word."C:CADENCEPSD_15,1TOOLSPR

22、OJECTS" -c"C:CadencePSD_15,1toolscaptureallegro.cfg" -v 3 -j "CC2430_DEMO"# 1 Error ALG0012 Property "PCB Footprint" missing from instance U3: SCHEMATIC1, PAGE1 (2.00, 2.10).# 2 Error ALG0012 Property "PCB Footprint" missing from instance C2: SCHEMATIC1,

23、PAGE1 (2.30, 0.30).# 17 Aborting Netlisting. Please correct the above errors and retry.错误解释：Error ALG0012 Property "PCB Footprint" missing from part <Part Reference>: <Schematic> , <Page> (<LocationX> , <LocationY)>A PCB Footprint (JEDEC_TYPE in Allegro) is re

24、quired for all parts in Allegro. Therefore all parts without this property are listed before aborting the netlisting. You can add the PCB Footprint property by selecting the part listed, then choosing Edit Properties from the pop-up menu and placing a value, such as dip14_3, on the part.在Allegro中，每个

25、器件都需要一个PC的装。所以在取消列出网 表之前，软件会列出所有没有此项的器件。你可以选择列出的器件 添加PC的装，然后选择Edit Properties来编辑器件的值。处理办法：在导出Netlist 之前，只需要保证每个器件都是有封装的，且器件 PCB Footprint值与对应的.dra 封装文件名一致。(13) . DRC0011 Reference is invalid for this partThe reference for the part is invalid. For example, this occurs when a part reference like U?A h

26、as not been updated. Update the part reference 。7 / 9word.Reference项不可随意修改。(14) Pin numbers do not match. Check device file.原因：原理图中的晶振给了两个管脚，而其封装却是四个管脚。原理图与PC的装对应原则：除了 PCB Footprint的名字要写对以外，还有一点，就是原理图的 元件的管脚数目一定要和封装的管脚数目必须一样。这里说的管 脚，包括了原理图中可能没有现实的 Power Pins,不包括封装中的 machanical pins ;另外，原理图和封装的对应关系是依

27、靠pinnumber来建立的，所以两者的相应的 pin number 一定要一样，而 pin number是不是数字并没有关系。(15) . ERROR(SPMHNI-191): Device/Symbol check error detected.WARNING(SPMHNI-337): Unable to load symbol 'HDR1X2' for device'B2S_HDR1X2_B2S': WARNING(SPMHUT-127): Could not find padstack 57S40DP.due to ERROR(SPMHDB-274): Unable to load flash symbol THS79X59X45X4X15 (Check PSMPATH setting for this symbol)." 原因：花焊盘Flash没有创建.fsm的symbol文件，或是该文件保 存路径与.psm文件不一致。二、 Allegro 导入 netlist 的时候报错 can not find symbol :出现Netrev succeeded即可，说明已没有error 了，可以直接打开 自动生成的.brd文件了。但此时 Updating Allegro PCB Editor Board仍然会有红叉，貌似还