WAT-Basic-Introduction教学课件

1、WAT-Basic-IntroductionWAT-Basic-Introduction教学课件教学课件Summary What is WAT? Why do we need WAT? What can and cant WAT do? WAT basic concept/device/Layout Manual WAT probe (4156) Q&AWhat is WAT? WAT is abbreviation for Wafer Acceptance Test. WAT is the last process in FAB. WAT is an important proces

2、s in FAB. decide whether the wafer go through an normal process, and ship to customer.Why do we need WAT? WAT can test individual device of street, not die or chip. WAT can check electric characters of individual device. WAT can monitor front process via electric characters of individual device. WAT

3、 can provide out device test data for consumer.What can and cant WAT do?What can and can t WAT do?.contTest pattern:1)Test Line/Test Key: Production monitor, located on the Scribe Line and will be destroyed after die saw. 2)Test Chip: Design Rule check/Yield monitor/Process Qualification, usually ch

4、ip size, for initial process technology development.WAT basic concept/device/layoutWAT basic concept/device/layout.contWAT basic concept/device/layout.contMOS key parameters: Vt and GmIdsatIoffVBDIsubDIBLGAMMASWINGGleak, Isubmax, Isubvg, Gleak2, SUBVTSLP, Vt1, Vt2, MFAC1, MFAC2, BETATypical WAT test

5、key layoutDevice parameter MOSPurpose: check transistor electrical character.Continuity and Spacing of Poly, MetalSpacingHighLowContinuityHigh = 1V,measureIh, R=V / ISpacing/Bridging. Step increase Voltage, Breakdown1uA leakage currentField DeviceN+N+N-N-P-WellSpacerContMetalGateDrainSourceSimplest

6、design of MOSRelax design ruleP+PWSourceBodyDrainGateContMetalLFoxPoly GateAAFoxPurpose: Check filed IsolationGate oxide integrityODPolyLarge Area Flat PatternSmall Area Flat PatternFinger PatternEdge rich PatternGOI Yield = e -D0 AY1 / Y2 = e -D0 (A1 - A2)Gate Oxide Breakdown, Insulation (Vbd)Gate

7、Oxide Breakdown VoltageAlways in reverse polarity as well type, V(-) on PWSweep Vg voltage, measure IgUntile | Ig | 1uA, Vg = VbdGate Oxide LeakageForce Vg = 5V, Measure IgSheet resistance (Rs_N+/P+/NW/Po)LWLWInterconnect LayerHighLowSheer Resistance, CD-Loss (Rs, Cd)Two terminal Sheet ResistanceFor

8、ce Vh = 1V, measure IhRs = Vh / Ih * W / L , R = * L / W* t , Rs = / t, unit : /CD LossRs1 = ( Vh1 / Ih1) / L * (W1 + W )Rs2 = ( Vh2 / Ih2) / L * (W2 + W )Note:The polarity of PN junctionN stands for N-type and should be reverse biased to build up potentialBarrier. N- V(+), P-V(-) Contact Resistance

9、 (Rc_N+, P+, Via)LowHighN+MetalContact Resistance (Rc)Two terminal Contact ResistanceForce Vh = 1V, measure IhRc = Vh / Ih * N, unit / eaN = Contact number #FoxFoxFoxCountRc_N+Non-Guassiandistribution Stack contact chain CT-Via resistance pattern :a)Purpose: To monitor stack contact Rc from CT to V1

10、 , mainly focus on MET/VIA overlay, and metal island process)L1L2L3S1S2S3CS1CS2RC_N+CT_V1: (1800 Counts)VD=1.8V, VB=0VMeasure: ID, then RC_N+CT_V1 = (VD/ID 900*RS_N+_2/100)/1800Id/Gm vs VgId/Gm vs Vg00.0010.0020.0030.0040.00500.511.522.533.54Vg(V)Vt=X-intercept - 0.5*0.05V (for NMOS)Vt=X-intercept -

11、 0.5*0.05V (for NMOS)Id(A)Gm(mho)X-intercept (L1X)Max GmIn linear region: In Saturation region:When Id =Idsat, Vd=VG-Vth, and So, 5 . 0)(21)(dthgmdthGGdVVVgVVVVIIdd0.5VgIVVmdgthTransistor WAT parameters and test condition:1. VTGm_N:VD=0.05V, VS=VB=0V,VG=0 to 0.8*1.8V, whereas 1.8V is VDDNextrapolate

12、 to VG at max slope, measure VTGm_N = VG(INTERCEPT) - 0.5*VD2. VTLIN_N:VD=0.05V, VS=VB=0V,VG=0 to 0.8*1.8V, whereas 1.8V is VDDNMeasure VTLIN_N=VG ID=0.1uA*(W/L)To simplify the calculation, the transistor was considered turned on when ID=0.1uA*(W/L)Typical Value:VTLIN_N_10/10 = 0.37VVTLIN_P_10/10= -

13、0.44VVTLIN_N_10/0.18= 0.44VVTLIN_P_10/0.18 = -0.5VVTLIN_N_0.22/10 = 0.31VVTLIN_P_0.22/10 = -0.41VVTLIN_N_0.22/0.18 = 0.36VVTLIN_P_0.22/0.18 = -0.5VVTLIN_N3.3_10/10 = 0.68VVTLIN_P3.3_10/10 = -0.73VVTLIN_N3.3_10/0.35 = 0.72VVTLIN_P3.3_10/0.35 = -0.68VVTLIN_N3.3_0.22/10 = 0.56VVTLIN_P3.3_0.22/10 = -0.6

14、8V3. VTSAT_N:VD=1.8V, VS=VB=0V,VG=0 to 0.8*1.8V, whereas 1.8V is VDDNMeasure VTSAT_N = VG ID=0.1uA*(W/L)VD=VDDN, to make sure that the transistor is working at the saturation status4. IDSAT_N: VD=VG=VDDN=1.8V, VS=VB=0, Measure IDSAT_N=ID (then divide by W in some calculation)Typical Value:IDSAT_N_10

15、/0.18 = 6mAIDSAT_P_10/0.18 = -2.59mA(600 uA/um)(-259 uA/um)IDSAT_N_0.22/10 = 4uAIDSAT_P_0.22/10 = -1.1uAIDSAT_N_0.22/0.18 = 180uAIDSAT_P_0.22/0.18 = -60AIDSAT_N3.3_10/0.35 = 6mAIDSAT_P3.3_10/0.35 = -3mAIDSAT_N3.3_0.22/10 = 7.58uAIDSAT_P3.3_0.22/10 = -1.61uA5. IOFF_NVD=1.1*1.8V, VG=VS=VB=0, Measure I

16、OFF_N = ID (then divide by W in some calculation)Typical Value:IOFF_N_10/0.18 = 60 pAIOFF_P_10/0.18 = -30 pAIOFF_N3.3_10/0.35 = 60 pAIOFF_P3.3_10/0.35 = -35 pA6. BVD_NVG=VS=VB=0V, VD = 1.8 To 3*VDDN, whereas, VDDN=1.8V or 3.3V, Measure BVD_N=VD ID=0.1uA*WTypical Value:BVD_N_10/0.18 = 4VBVD_P_10/0.18

17、 = -5.21VBVD_N3.3_10/0.35 = 7VBVD_P3.3_10/0.35 = -6.99V7. ISUB_NVD=1.1*1.8V, VS=VB=0, VG = 0.2*1.8V to 1.1*1.8V, Find ISUB_N (MAX)(then, divided by W in some calculation) Monitor the hot carrier effect, Sweep Vg and Measure Ib. Isub=Abs(Isub)maxIThe substrate current in an n-channel MOSFET results f

18、rom hole generation by impact ionizations induced by the channel electrons traveling from source to drain. Assuming impact ionization occurs uniformly in the pinch off region (near the drain), the substrate current, Ibs, may be written as Ibs=Id Lwhere = ionization coefficient L= length of pinch off

19、 regionWith Vg, Ibs , and reaches a miximum value, then decrease.The initial Ibs increase is due to the increase in Id with Vg. However, as Vg goes up, the lateral field decreases, causing a reduction in . Thus, the peak substrate current occurs when the two competing factors cancel out, usually at

20、0.5Vd.Typical Value:ISUB_N_10/0.18= ( 1.6 uA )ISUB_P_10/0.18 = ( -0.013 uA ) 8. DIBL (Drain Induced Barrier Lowering)VTLINVD=0.05V, VS=VB=0, VG = 0 to 0.8*VDDNMeasure VTLIN=VG ID = 0.1A*(W/L)VTSATVD=1.1*VDDN, VS=VB=0, VG = 0 to 0.8*VDDNMeasure VTSAT=VGID = 0.1A*(W/L)DIBL= (VTLIN-VTSAT) / (1.1*VDDN-0

21、.05)Threshold variation is caused by the increased current with increased drain voltage, as the applied drain voltage controls the inversion layer charge at the drain, thereby competing with the gate voltage. In the weak inversion regime, there is a potential barrier between the source and the chann

22、el region. The height of this barrier is a result of the balance between drift and diffusion current between these two regions. If a high drain voltage is applied, the barrier height can decrease, leading to an increase drain current. Thus the drain current is controlled not only by gate voltage, bu

23、t also by the drain voltage. 9. GAMMA_N ( : body effect) VD=0.05V, VS=0, VB=-1.5*1.8, VG=0 to 1.1*1.8 Measure VTLIN1_N = VG ID=0.1uA*(W/L) the threshold voltage with substrate bias ( VB) =0.443744GAMMA_N=ABS (VTLIN1_N-VTLIN_N) / ASB(VB)+2* 1/2-2* 1/2 Since, VT = GC-QB/Cox-2 B-Qox/Cox = VFB-2 B+ SQRT

24、(-2 B+VB) Where: VFB= GC-Qox/Coxand =SQRT(2siqNB)/Cox VTLIN1=VFB-2 B+ SQRT(-2 B+VB)VTLIN = VFB-2 B+ SQRT(-2 B) =(VTLIN1-VTLIN)/SQRT(-2 B+VB)- SQRT(-2 B)Typical Value:GAMMA_N_10/10 = 0.5 V1/2GAMMA_P_10/10 = 0.57 V1/210. SWING_NVD=0.05V, VS=VB=0, VG = 0 to 1.8V, Measure VG1 ID = 10 nA *(W/L) VG2 ID =

25、0.1 nA * (W/L)SWING_N = 500* (VG1-VG2)In the week inversion (or sub-threshold) regime, the transistor conducts a very small sub-threshold current, and the drain current depends exponentially on the gate-source voltage. To measure the sub-threshold slope, SS, when VD=0.05V, is defined as:SUBVTSLP=(sl

26、ope)-1=(VG1-VG2 )/log (Ileak1) log (Ileak2) = (VG1-VG2 )/ log(Ileak1/Ileak2) V/dec= (VG1-VG2 )/ log(10/0.1) V/dec= (VG1-VG2 )/ 2 V/dec= 500* (VG1-VG2 ) mV/decIleak1= 10nA*(W/L)Ileak2=0.1nA*(W/L)VG2 VG111. Gleak_NVS=VD=VB=0,VG= - VDDN=-1.8V, Measure IG. If 50nA, consider Transistor fail the test, ski

27、p all rest transistor tests12. Gm_NMax slope of ID vs VG VB=013. VsubvgVD= 1.1*VDDN,VB=VS=0,VG=0.2*VDDN to 0.7*VDDNMeasure VG max ISUBtest itempurposetest conditionFailureFailure suspected process suspected processTypicalTypicalvaluevalueTypical curve Typical curve VTLIN_N To monitor ID changedby VG

28、 in liner area.To measureVT(VTLINID=0.1uA*(W/L) when transistor wasconsidered turned onVD=0.05V, VS=VB=0V,VG=0V TO 0.8*1.8V MeasureVTLIN_N=VG ID=0.1uA*(W/L)PWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL,GATE2 OXIDEPRECLEAN, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,Gate2 reoxidation, NPOCKETIMP, NL

29、DD1 IMP,SPACE PROCESS,N+ IMP,SAB Process, Salicideprocess0.44V(10/0.18);0.36V(0.22/0.18);VTGm_N To monitor the speedthat IDis changed byVG. Measure VTGm(at maxdifferential ID and VG)to conform the pointwhere the transistorwas turned on.VD=0.05V,VS=VB=0V,VG=0V TO 0.8*1.8VExtrapolate to VG at maxslope

30、, Measure VTGM_N=VG(INTERCEPT)-0.5*VDPWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL,GATE2 OXIDEPRECLEAN, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,Gate2 reoxidation, NPOCKETIMP, NLDD1 IMP,SPACE PROCESS,N+ IMP,SAB Process, Salicideprocess0.56V(10/0.18);180uA(0.22/0.18)VTSAT_N To monitor ID changedby

31、 VG in saturationarea. Measure VTSATwhen the transistorworked in saturationareaVD=1.8V,VS=VB=0V, VG=0V TO0.8*1.8V Measure VTSAT_N=VGID=0.1uA*(W/L)PWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL,GATE2 OXIDEPRECLEAN, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,Gate2 reoxidation, NPOCKETIMP, NLDD1 IMP,SP

32、ACE PROCESS,N+ IMP,SAB Process, Salicideprocess0.36V(10/0.18)IDSAT_N To monitor ID changedby VG in saturationarea. Measure ID whenthe transistor workedin saturation areaVD=1.8V, VS=VB=0V, VG=1.8V MeasureIDSAT_N=IDPWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL, Gate2reoxidation, Gate2 oxide, POLYDEP,

33、GATE PHOTO, POLY ETCH,NPOCKET IMP, NLDD1 IMP,SPACEPROCESS, N+ IMP,SAB Process,Salicide process6mA(10/0.18)IOFF_N To monitor leakagebetween source anddrain when VG=0V ofshort channel NMOStransistor.VD=1.1*1.8V,VS=VG=VB=0V, Measure IOFF_N=IDPWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL, Gate2reoxidati

34、on, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,NPOCKET IMP, NLDD1 IMP,SPACEPROCESS, N+ IMP,SAB Process,Salicide process60pA(10/0.18)0.00E+001.00E-042.00E-043.00E-044.00E-045.00E-046.00E-047.00E-048.00E-049.00E-0400.511.522.50.00E+002.00E-044.00E-046.00E-048.00E-041.00E-031.20E-0300.511.522.50.00E+0

35、01.00E-032.00E-033.00E-034.00E-035.00E-036.00E-037.00E-038.00E-0300.511.522.50.00E+001.00E-032.00E-033.00E-034.00E-035.00E-036.00E-037.00E-038.00E-0300.511.522.50.00E+002.00E-104.00E-106.00E-108.00E-101.00E-091.20E-090123456test itempurposetest conditionFailureFailure suspected process suspected pro

36、cessTypicalTypical value valueTypical curve Typical curve VBD_N To monitor ID changedby VD when VG=0V ofshort channelNMOS transistor. Measure the voltagewhen source and drainwas broken down.VG= VS=VB=0V, VD=1.8V to3*1.8V. MeasureVBD_N=VDID=0.1uA*WPWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL,GATE2 O

37、XIDEPRECLEAN, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,Gate2 reoxidation, NPOCKETIMP, NLDD1 IMP,SPACE PROCESS,N+ IMP,SAB Process, Salicideprocess 4V ISUB_N To monitor hot carriereffect between sourceand drain of shortchannel NMOS transistorVD=1.1*1.8V, VS=VB=0V,VG=0.2*1.8V to 1.1*1.8VFIND ISUB_N(

38、MAX)PWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL,GATE2 OXIDEPRECLEAN, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,Gate2 reoxidation, NPOCKETIMP, NLDD1 IMP,SPACE PROCESS,N+ IMP,SAB Process, Salicideprocess1.6uA(10/0.18)DIBL_N To monitor Draininduced BarrierLowering effectbetween source anddrain of s

39、hort channelNMOS transistor VTLIN: VD=0.05V,VS=VB=0V, VG=0V TO 0.8*1.8VMeasure VTLIN=VGID=0.1uA*(W/L);VTSAT: VD=1.1*1.8V,VS=VB=0V, VG=0V to 0.8*1.8V MeasureVTSAT=VGID=0.1uA*(W/L)PWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL,GATE2 OXIDEPRECLEAN, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,Gate2 reoxi

40、dation, NPOCKETIMP, NLDD1 IMP,SPACE PROCESS,N+ IMP,SAB Process, Salicideprocess0.04(10/0.18)GAMMA_N To monitor hot carriereffectbetween source anddrain of short channelNMOS transistorVD=0.05V, VS=0V, VB=-1.5*1.8V, VG=0V to 1.1*1.8V,MeasureVG=VTLIN1_NID=0.1uA*(W/L);f=0.443744GAMMA_N=ABS(VTLIN1_N-VTLI

41、N_N)/(ABS(VB)+2*f)1/2-(2*f)1/2)PWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL, Gate2reoxidation, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,NPOCKET IMP, NLDD1 IMP,SPACEPROCESS, N+ IMP, SAB Process,Salicide process0.326(10/0.18)SWING_N To monitor sub-threshold slope of short channel NMOStransistorVD=

42、0.05, VS=VB=0V, VG=0V to1.8VMeasure VG1ID=1E-8*(W/L),VG2ID=1E-10*(W/L)AWING_N=500*(VG1-VG2)PWELL IMP, NCHANNEL IMP, VTNIMP, NWELL ANNEAL,GATE2 OXIDEPRECLEAN, Gate2 oxide, POLYDEP, GATE PHOTO, POLY ETCH,Gate2 reoxidation, NPOCKETIMP, NLDD1 IMP,SPACE PROCESS,N+ IMP,SAB Process, Salicideprocess88mV/dec

43、(10/0.18)0.00E+002.00E-104.00E-106.00E-108.00E-101.00E-091.20E-0901234560.00E+002.00E-064.00E-066.00E-068.00E-061.00E-051.20E-050123456-3.00E-06-2.50E-06-2.00E-06-1.50E-06-1.00E-06-5.00E-070.00E+0000.511.522.5Gate capacitor key parameters:1) TOX,2) Leakage 3) Breakdown Voltage4) CapWAT basic concept

44、/device/layout.conttest itempurposetest conditionFailure suspectedFailure suspectedprocessprocessTypicalTypicalvaluevalueTOX/PW_BKTo monitor thin gateoxideintegrate on Pwell100KHZ, 45mV,VG=GND,VB=1.1*1.8V measure CAP,TOX/PW=3.9*8.85418*7000/CAP STI LINING OXIDE, HIGHTEMP ANN, STI HDP OXDEP, STI RTA,

45、 GATE2OXIDE PRECLEAN, GATE1OXIDE46AILOX/PW_BKTo monitor thin gateoxideintegrate on PwellVG=-1.8V,VB=0Vmeasure ILOX/PW_BK=IG STI LINING OXIDE, HIGHTEMP ANN, STI HDP OXDEP, STI RTA, GATE2OXIDE PRECLEAN, GATE1OXIDE65.5pABVOX/PW_BKTo monitor thin gateoxideintegrate on PwellVB=0V,VG=-1.8V TO 4*-1.8V MEAS

46、UREBVOX_PW=VGIG=-1uASTI LINING OXIDE, HIGHTEMP ANN, STI HDP OXDEP, STI RTA, GATE2OXIDE PRECLEAN, GATE1OXIDE-3.78VWAT basic concept and device.contDiode Key Parameters:Capacitor Leakage1) Breakdown voltagetest itempurposetest conditionFailure suspectedFailure suspectedprocessprocessTypicalTypicalvalu

47、evalueCJ/PW_F1.8To monitor the junctionCapacitor betweenN+AA and Pwell withfinger pattern100KHZ, 45mV, VD=GND,VB=0VmeasureCJ/PW_F1.8ID=CAPAA PHOTO, AAETCH, STILINING OXIDE, HIGH TEMPANN, STI HDP OX DEP, STIRTA,STI CMP, PWELL IMP,NCHANNEL IMP, VTN IMP,NWELL ANNEAL,NLDD1 IMP,N+IMP3.72PFIJ/PW_F1.8To mo

48、nitor the junctionleak from N+ to Pwellwith finger patternVD=1.1*1.8V, VB-OV measure IJ/PW_F1.8=IDAA PHOTO, AAETCH, STILINING OXIDE, HIGH TEMPANN, STI HDP OX DEP, STIRTA,STI CMP, PWELL IMP,NCHANNEL IMP, VTN IMP,NWELL ANNEAL,NLDD1 IMP,N+IMP8pABJ/PW_F1.8To monitor the junctionbreakdown voltagefrom N+

49、to Pwell withfinger patternVB=OV, VD=1.8V TO 15VmeasureBJ/PW_F1.8=VDID=1uAAA PHOTO, AAETCH, STILINING OXIDE, HIGH TEMPANN, STI HDP OX DEP, STIRTA,STI CMP, PWELL IMP,NCHANNEL IMP, VTN IMP,NWELL ANNEAL,NLDD1 IMP,N+IMP11.6VPolyM1CTsalicideP+Test condition:VD=-0.2V, VB=0V Measure: ID & Compute Rs=(VD/ID)/(L/W)P+ Poly resistance pattern : RSFV_PP_D15_400(OHM/SQ.)RSFV_PP_D15_400