试验三--8-3优先编码器和8线译码器讲解学习

1、实验三 8-3优先编码器和3-8线译码器 、实验目的1、熟悉常用编码器，译码器的功能逻辑。2、熟悉VHDL的代码编写方法。3、掌握复杂译码器的设计方法。、实验原理1、8-3线优先编码器的真值表。X1X2X3X4X5X6X7X8Y2Y1Y0XXXXXX0X000XXXXX01X001XXXX011X010XXX0111X011XX0X100X01111X1010111111X1101111111X1112、逻辑表达式：Y2=X4&X5&X6&X7丫仁 (X2 )&X4&X5|(X3)&X4&X5|(X6)|(X7);Y0=(X1) &

2、;X2&X4& X6|(X3) &X4& X6|(X5) &X6|(X7);2、3-8线码器总体思路以EP2C5中的三个拨位开关，SW3, SW2,SW1为三个输入信号，可以代表 8种 不同的状态，该译码器对这 8种状态译码，并把所译码的结果在七段LED数码管上显示出来。三、实验连线1、 将EP2C5适配板左下角的 JTAG用十芯排线和万用下载区左下角的SOPC JTAG 口连接起来，万用下载区右下角的电源开关拨到SOPC下载的一边2、 请将JPLED1短路帽右插，JPLED的短路帽全部上插。3、请将JP103的短路帽全部插上。四、实验步骤及波形按照步骤

3、三正确连线，参考实验二步骤，完成项目的建立，文件的命名，文件的编辑， 语法检查，引脚分配，编译，下载。8-3优先编码器参考代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY encode ISPORT(XINA :IN STD_LOGIC_VECTOR(7 DOWNTO 0);Y0,Y1,Y2: OUT STD_LOGIC;OUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);LEDW: OUT S

4、TD_LOGIC_VECTOR(2 DOWNTO 0);END en code;ARCHITECTURE ADO OF encode ISSIGNAL LED: STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL XIN: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINXIN<=XINA;LEDW<="000"PROCESS (XIN)BEGINCASE XIN ISWHEN x"00"WHEN x"01"WHEN x"02"WHEN x"04&quo

5、t;WHEN x"08"WHEN x"10"WHEN x"20"WHEN x"40"WHEN x"80"> OUTA<=x"3F"> OUTA<=x"06"> OUTA<=x"5B"> OUTA<=x"4F"> OUTA<=x"66"> OUTA<=x"6D"> OUTA<=x"7D&

6、quot;> OUTA<=x"07"> OUTA<=x"3F"WHEN OTHERS => OUTA<=x"3F"END CASE; END PROCESS; PROCESS (XIN) BEGINCASE XIN IS> LED<="001"> LED<="010"> LED<="011"> LED<="100"> LED<="101"&g

7、t; LED<="110"> LED<="111"> LED<="000"WHEN x"01"WHEN x"02"WHEN x"04"WHEN x"08"WHEN x"10"WHEN x"20"WHEN x"40"WHEN x"80"WHEN OTHERS => LED<="000"END CASE;END PROC

8、ESS; Y2<=LED(2);Y1<=LED(1);Y0<=LED(0);END ADO;3-8 译码器参考代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY DECODE ISPORT(DATA_IN :IN STD_LOGIC_VECTOR(2 DOWNTO 0); LEDOUT,DATA_OUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);LEDW :OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );END DECOD

9、E; ARCHITECTURE ADO OF DECODE ISSIGNAL OUTA,D_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGINLEDW<="000"PROCESS (DATA_IN)VARIABLE DIN: STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINDIN:=DA TA_IN;LEDOUT<=OUTA; DATA_OUT<=D_OUT;CASE DIN ISwhen "000"=>OUTA<="00111111"-"0&

10、quot;when "001"=>outa<="00000110"-"1"when "010"=>outa<="01011011"-"2"whe n "011"=>outa<="01001111"-"3"whe n "100"=>outa<="01100110"-"4"when "101"=

11、>outa<="01101101"-"5"whe n "110"=>outa<="01111101"-"6"whe n "111"=>outa<="00000111"-"7"WHEN OTHERS => OUTA<="XXXXXXXX" END CASE;CASE DIN ISWHEN "000" => D_OUT<="0000

12、0000"WHEN "001" => D_OUT<="00000001"WHEN "010" => D_OUT<="00000010"WHEN "011" => D_OUT<="00000100"WHEN "100" => D_OUT<="00001000"WHEN "101" => D_OUT<="00010000"WHEN

13、"110" => D_OUT<="00100000"WHEN "111" => D_OUT<="01000000"WHEN OTHERS=> D_OUT<="XXXXXXXX" END CASE;END PROCESS;END ADO;五、实验仿真8-3编码器引脚锁定如图:*恤tcjy ArtF 蚊 Pns:d-口 wLan'itef >oupiHti5i3rdardPe-aTii&i1O" LzRhDCutpitP1UJ4L3

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