湘潭大学计算机原理实验四多周期MIPSCPU+存储器实验预习报告

1、实验四 多周期MIPS CPU +存储器实验一实验目的1、深入理解MIPSCPU指令系统的功能和工作原理；2、掌握多周期CPU的工作原理和逻辑功能实现；3、熟练掌握用Verilog HDL语言设计多周期存储器的方法；4、熟练掌握对多周期存储器的仿真实验验证和硬件测试两种调试方法；5、通过对多周期CPU的运行情况进行观察和分析，进一步加深理解。二实验设备硬件：现代计算机组成原理实验系统（兼）Nios 32位嵌入式系统实验开发平台 EP1C12Q240Core（TM）i3-3240 CPU3.40GHz 3.39GHz 1.91GB的内存软件：QuartusII 13.0sp1 Microsoft

2、 Windows xp三实验内容1、设计一个32位MIPS多周期CPU具体的要求如下: 至少运行下列的6类32条MIPS指令。 （1）算术逻辑指令and、sub、addi （2）逻辑运算指令and、0r、xor、 andi、 ori、xori（3）位移指令sll、srl、sra（4）条件分支指令beq、bne、（5）无条件跳转指令j、jr （6）数据传送指令lw、sw2.设计一个存储器四实验原理与步骤实现上述原理框图根据功能将其分划分为控制单元(cunit)、执行单元(eunit)、指令单元(iunit)以及存储单元(munit)四大模块。 （1）.控制单元(cunit)是多周期微处理器的核心

3、控制微处理器取指令、指令译码和指令执行等工作。主要由指令译码器控制器(outputs control)、算术逻辑运算控制器(ALU control)两个子模块组成。 （2）.执行单元(eunit)主要由寄存器堆(registers)和算术逻辑单元(ALU)两个子模块组成。其中寄存器是微处理器最基本的元素MIPS系统的寄存器堆由32个32位寄存器组成而ALU则是微处理器的主要功能部件执行加、减、比较等算术运算和与、或、或非、异或等逻辑运算。指令单元(iunit)的作用是决定下一条指令的地址PC值。 （3）.存储单元(munit)由存储器(memory)、指令寄存器(instruction reg

4、ister)和存储数据寄存器(memory data register)组成。五实验源代码寄存器元件代码：module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb);input4:0rna,rnb,wn;input31:0d;inputwe,clk,clrn;output31:0qa,qb;reg31:0register1:31;/r1-r31assign qa = (rna = 0) ? 0 : registerrna;/readassign qb = (rnb = 0) ? 0 : registerrnb;/readalways (posedge clk

5、 or negedge clrn) beginif (clrn = 0) begin/resetinteger i;for (i=1; i<32; i=i+1)registeri <= 0;endelse beginif (wn != 0) && (we = 1)/writeregisterwn <= d;endendendmodule32位四选一选择器：module mux4x32 (a0,a1,a2,a3,s,y);input 31:0a0,a1,a2,a3;input1:0s;output31:0y;function31:0select;input 31

6、:0a0,a1,a2,a3;input 1:0s;case (s)2'b00:select=a0;2'b01:select=a1;2'b10:select=a2;2'b11:select=a3;endcaseendfunctionassigny=select (a0,a1,a2,a3,s);endmodule5位二选一选择器：module mux2x5 (a0,a1,s,y);input 4:0a0,a1;inputs;output4:0y;assigny = s ? a1 : a0;endmodule32位二选一选择器：module mux2x32 (a0,a

7、1,s,y);input 31:0a0,a1;inputs;output31:0y;assigny = s ? a1 : a0;endmodule存储器元件：module mcmem (clk, dataout, datain, addr, we, inclk, outclk);input31:0 datain;input31:0 addr;inputclk, we, inclk, outclk;output31:0dataout;wirewrite_enable = we & clk;lpm_ram_dqram (.data(datain),.address(addr7:2),.we

8、(write_enable),.inclock(inclk),.outclock(outclk),.q(dataout);defparamram.lpm_width=32;defparam ram.lpm_widthad=6;defparamram.lpm_indata="registered"defparamram.lpm_outdata="registered"defparamram.lpm_file="mcmem.mif"defparamram.lpm_address_control="registered"

9、endmodule控制部件：module mccu (op, func, z, clock, resetn, wpc, wir, wmem, wreg, iord, regrt, m2reg, aluc, shift, alusrca, alusrcb, pcsource, jal, sext, state);input5:0op, func;inputz, clock, resetn;output regwpc, wir, wmem, wreg, iord, regrt, m2reg;output reg3:0aluc;output reg1:0alusrcb, pcsource;outpu

10、t regshift, alusrca, jal, sext;output reg2:0state;reg2:0next_state;parameter2:0sif=3'b000,/ IF statesid=3'b001,/ ID statesexe=3'b010,/ EXE statesmem=3'b011,/ MEM stateswb=3'b100;/ WB statewire r_type,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,i_jr;wire i_addi,i_andi,i_ori,i_x

11、ori,i_lw,i_sw,i_beq,i_bne,i_lui,i_j,i_jal;and(r_type,op5,op4,op3,op2,op1,op0);and(i_add,r_type, func5,func4,func3,func2,func1,func0);and(i_sub,r_type, func5,func4,func3,func2, func1,func0);and(i_and,r_type, func5,func4,func3, func2,func1,func0);and(i_or, r_type, func5,func4,func3, func2,func1, func0

12、);and(i_xor,r_type, func5,func4,func3, func2, func1,func0);and(i_sll,r_type,func5,func4,func3,func2,func1,func0);and(i_srl,r_type,func5,func4,func3,func2, func1,func0);and(i_sra,r_type,func5,func4,func3,func2, func1, func0);and(i_jr, r_type,func5,func4, func3,func2,func1,func0);and(i_addi,op5,op4, o

13、p3,op2,op1,op0);and(i_andi,op5,op4, op3, op2,op1,op0);and(i_ori, op5,op4, op3, op2,op1, op0);and(i_xori,op5,op4, op3, op2, op1,op0);and(i_lw, op5,op4,op3,op2, op1, op0);and(i_sw, op5,op4, op3,op2, op1, op0);and(i_beq, op5,op4,op3, op2,op1, op0);and(i_bne, op5,op4,op3, op2,op1, op0);and(i_lui, op5,op

14、4, op3, op2, op1, op0);and(i_j, op5,op4,op3,op2, op1,op0);and(i_jal, op5,op4,op3,op2, op1, op0);wire i_shift;or (i_shift,i_sll,i_srl,i_sra);always * begin/ control signals' dfault outputs:wpc=0;/do not write pcwir=0;/do not write irwmem=0;/ do not write memorywreg=0;/ do not write register filei

15、ord=0;/ select pc as memory addressaluc=4'bx000;/ ALU operation: addalusrca=0;/ ALU input a: reg a or saalusrcb=2'h0;/ ALU input b: reg bregrt=0;/ reg dest no: rdm2reg=0;/ select reg cshift=0;/ select reg apcsource=2'h0;/ select alu outputjal=0;/ not a jalsext=1;/ sign extendcase (state)

16、/- IF:sif: begin/ IF statewpc=1;/ write pcwir=1;/ write IRalusrca=1;/ PCalusrcb=2'h1;/ 4next_state=sid;/ next state: IDend/- ID:sid: begin/ ID stateif (i_j) begin/ j instructionpcsource=2'h3;/ jump addresswpc=1;/ write PCnext_state=sif;/ next state: IFendelse if (i_jal) begin/ jal instructio

17、npcsource=2'h3;/ jump addresswpc=1;/ write PCjal=1;/ reg no = 31wreg=1;/ save PC+4next_state=sif;/ next state: IFendelse if (i_jr) begin/ jr instructionpcsource=2'h2;/ jump registerwpc=1;/ write PCnext_state=sif;/ next state: IFendelse begin/ other instructionaluc=4'bx000;/ addalusrca=1;

18、/ PCalusrcb=2'h3;/ branch offsetnext_state=sexe;/ next state: EXEendend/- EXE:sexe: begin/ EXE statealuc3=i_sra;aluc2=i_sub | i_or | i_srl | i_sra | i_ori | i_lui ;aluc1=i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne | i_lui ;aluc0=i_and | i_or | i_sll | i_srl | i_sra | i_andi | i_ori ;i

19、f (i_beq | i_bne) begin/ beq or bne instructionpcsource=2'h1;/ branch addresswpc=i_beq & z | i_bne & z;/ write PCnext_state=sif;/ next state: IFendelse begin/ other instructionif(i_lw | i_sw) begin/ lw or sw instructionalusrcb=2'h2;/ select offsetnext_state=smem;/ next state: MEMende

20、lse begin/ other instructionif (i_shift)shift=1;/ shift instructionif (i_addi | i_andi | i_ori | i_xori | i_lui)alusrcb=2'h2;/ select immediateif (i_andi | i_ori | i_xori)sext=0;/ 0-extendnext_state=swb;/ next state: WBendendend/- MEM:smem: begin/ MEM stateiord=1;/ memory address = Cif (i_lw) be

21、ginnext_state=swb;/ next state: WBendelse begin/ storewmem=1;/ write memorynext_state=sif;/ next state: IFendend/- WB:swb: begin/ WB stateif (i_lw)m2reg=1;/ select memory dataif (i_lw | i_addi | i_andi | i_ori | i_xori | i_lui)regrt=1;/ reg dest no: rtwreg=1;/ write register filenext_state=sif;/ nex

22、t state: IFend/- ENDdefault: beginnext_state=sif;/default stateendendcaseendalways (posedge clock or negedge resetn) begin/ state registersif (resetn = 0) beginstate<=sif;endelse beginstate<=next_state;endendendmodule32位带使能端触发器：module dffe32 (d,clk,clrn,e,q);input31:0d;inputclk,clrn,e;output31

23、:0q;reg31:0q;always (negedge clrn or posedge clk)if (clrn = 0) beginq <= 0;endelse beginif(e = 1)q <= d;endendmodule32位触发器：module dff32 (d,clk,clrn,q);input31:0d;inputclk,clrn;output31:0q;reg31:0q;always (negedge clrn or posedge clk)if (clrn = 0) beginq <= 0;endelse beginq <= d;endendmod

24、uleALU计算部件：module alu (a,b,aluc,r,z);input 31:0 a,b;input 3:0 aluc;output 31:0 r;output z;assign r = cal(a,b,aluc);assign z = |r;function 31:0 cal;input 31:0 a,b;input 3:0 aluc;casex (aluc)4'bx000: cal=a+b;4'bx100: cal=a-b;4'bx001: cal=a&b;4'bx101: cal=a|b;4'bx010: cal=ab;4&#

25、39;bx110: cal=b15:0,16'h0;4'bx011: cal=b<<a4:0;4'b0111: cal=b>>a4:0;4'b1111: cal=$signed(b)>>>a4:0;endcaseendfunctionendmodule其他部件：module f (reg_dest,jal,wn);input4:0reg_dest;input jal;output4:0wn;assignwn=reg_dest | 5jal;endmodulemodule sa (di,dot);input 4:0 di;

26、output 31:0 dot;assign dot = 27'b0,di;endmodulemodule out4 (out);output 31:0 out;assign out = 32'h4;endmodulemodule e (immin,sext,immediate,offset);input15:0immin;inputsext;output31:0 immediate,offset;wire e=sext & immin15;wire15:0imm=16e;assignoffset =imm13:0,immin15:0,1'b0,1'b0

27、;assignimmediate= imm,immin15:0;endmodulemodule combine (address,pc,add);input25:0address;input3:0pc;output31:0add;assignadd=pc3:0,address25:0,1'b0,1'b0;endmodulemodule convert1 (dain,sain,op,func,rs,rt,rd,imm,addr);input31:0dain;output4:0sain,rs,rt,rd;output5:0op,func;output15:0imm;output25

28、:0addr;assignsain=dain10:6;assignop=dain31:26;assignfunc=dain5:0;assignrs=dain25:21;assignrt=dain20:16;assignrd=dain15:11;assignimm=dain15:0;assignaddr=dain25:0;endmodulemodule convert2 (pc,pcout);input31:0pc;output3:0pcout;assignpcout=pc31:28;endmodule存储器内的测试数据：- Copyright (C) 1991-2013 Altera Corp

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31、ctured by Altera and sold by - Altera or its authorized distributors. Please refer to the - applicable agreement for further details.- Quartus II generated Memory Initialization File (.mif)DEPTH = 64;%Memory depth and width are required%WIDTH = 32;%Enter a decimal number%ADDRESS_RADIX = HEX;%Address

32、 and value radixes are optional%DATA_RADIX = HEX;%Enter BIN, DEC, HEX, or OCT; unless%otherwise specified, radixes = HEX%CONTENT BEGIN0.3F : 00000000;% Range-Every address from 0 to 3F = 00000000% 0 : 3c010000;% (00)main:luir1,0# address of data0% 1 : 34240080;% (04)orir4,r1,0x80# address of data0%

33、2 : 20050004;% (08)addir5,r0,4# counter% 3 : 0c000018;% (0c)call:jalsum# call function% 4 : ac820000;% (10)swr2,0(r4)# store result% 5 : 8c890000;% (14)lwr9,0(r4)# check sw% 6 : 01244022;% (18)subr8,r9,r4# sub: r8 <- r9 - r4% 7 : 20050003;% (1c)addir5,r0,3# counter% 8 : 20a5ffff;% (20)loop2:addir

34、5,r5,-1# counter - 1% 9 : 34a8ffff;% (24)orir8,r5,0xffff# zero-extend: 0000ffff% A : 39085555;% (28)xorir8,r8,0x5555# zero-extend: 0000aaaa% B : 2009ffff;% (2c)addir9,r0,-1# sign-extend: ffffffff% C : 312affff;% (30)andir10,r9,0xffff# zero-extend: 0000ffff% D : 01493025;% (34)orr6,r10,r9# or: ffffffff% E : 01494026;% (38)xorr8,r10,r9# xor: ffff0000% F : 01463824;% (3c)andr7,r10,r6# and: 0000ffff% 10 : 10a00001;% (40)beqr5,r0,shift# if r5 = 0, goto shift% 11 : 08000008;% (44)jloop2# jumploop2% 12 : 2005ffff;% (48)shift:addir5,r0,-1# r5 = ffffffff% 13 : 000543c0;% (4c)sllr8,r5,15# <&l