DRAM和存储器

1、ECE 4100/6100Advanced Computer Architecture Lecture 11 DRAM and StorageProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringGeorgia Institute of Technology2The DRAM CellWhy DRAMs Higher density than SRAMsDisadvantages Longer access times Leaky, needs to be refreshed Cannot be easily

2、 integrated with CMOSStack capacitor (vs. Trench capacitor)Source: Memory Arch Course, Insa. ToulouseWord Line (Control)Storage CapacitorBit Line (Information)1T1C DRAM cell3One DRAM BankwordlinebitlinesSense ampsI/O gatingRow decoderColumn decoderData outAddress4Column decoderColumn decoderColumn d

3、ecoderRow decoderRow decoderRow decoderExample: 512Mb 4-bank DRAM (x4)Sense ampsI/O gatingRow decoderColumn decoderData out D3:0AddressA13:0A10:0Address Multiplexing16K2kA x4 DRAM chipA DRAM page = 2kx4 = 1KBBA1:0Bank016384 x 2048 x 45DRAM Cell ArrayWordline0Wordline1Wordline2Wordline1023bitline0bit

4、line1bitline2bitline15Wordline36DRAM Sensing (Open Bitline Array)WL0WL1WL2WL127A DRAM SubarryWL128 WL129WL130WL255A DRAM Subarry7Basic DRAM OperationsVdd/2WLBLVdd/2VddWrite 1driverVdd - VthVdd/2WLBLPrecharge to Vdd/2Vdd/2 + VsignalRead 1Vdd - VthBLmmddsignalCCC2VVCmCBLAmplified Vsignalrefresh8DRAM B

5、asics Address multiplexingSend row address when RAS asserted Send column address when CAS asserted DRAM reads are self-destructiveRewrite after a read Memory arrayAll bits within an array work in unison Memory bankDifferent banks can operate independently DRAM rankChips inside the same rank are acce

6、ssed simultaneously9Examples of DRAM DIMM StandardsD0D7x8D8D15x8D16D23x8D24D31x8D32D39x8D40D47x8D48D55x8D56D63x8x64 (No ECC)D0D7x8D8D15x8CB0CB7x8D16D23x8D24D31x8D32D39x8D40D47x8D48D55x8X72 (ECC)D56D63x810DRAM Ranksx8x8x8x8x8x8x8x8x8x8x8x8x8x8x8x8D0D7D8D15D16D23D24D31D32D39D40D47D48D55D56D63CS1CS0Mem

7、ory Controller11DRAM RanksSingle Rank8b8b8b8b8b8b8b8b64bSingle Rank4b4b4b4b4b4b4b4b64b4b4b4b4b4b4b4b4bDual-Rank8b8b8b8b8b8b8b8b64b64b8b8b8b8b8b8b8b8b12DRAM OrganizationSource: Memory Systems Architecture Course, B. Jacobs, Maryland13Organization of DRAM ModulesSource: Memory Systems Architecture Cou

8、rse Bruce Jacobs, University of MarylandMemoryControllerAddr and Cmd BusData BusChannelMulti-Banked DRAM Chip14DRAM Configuration ExampleSource: MICRON DDR3 DRAM15MemoryControllerDRAM ModuleAddr BusWECASRASAssert RASRow AddressRow OpenedData BusColumn AddressAssert CASDRAM Access (Non Nibble Mode)RA

9、SCASADDRDATARow AddrCol AddrDataCol AddrData16DRAM Refresh Leaky storage Periodic Refresh across DRAM rows Un-accessible when refreshing Read, and write the same data back Example: 4k rows in a DRAM100ns read cycleDecay in 64ms4096*100ns = 410s to refresh once410s / 64ms = 0.64% unavailability17DRAM

10、 Refresh Styles Bursty64ms410s =(100ns*4096)410s64ms Distributed64ms15.6s64ms100ns18 RAS-Only Refresh CAS-Before-RAS (CBR) RefreshMemoryControllerDRAM ModuleDRAM ModuleMemoryControllerAddr BusWECASRASAddr BusWE#CASRASAssert RASRow AddressRefresh RowAssert RASRefresh RowAssert CASWE HighIncrement cou

11、nterDRAM Refresh Policies Addr counterNo address involved19Types of DRAMAsynchronous DRAM Normal: Responds to RAS and CAS signals (no clock) Fast Page Mode (FPM): Row remains open after RAS for multiple CAS commands Extended Data Out (EDO): Change output drivers to latches. Data can be held on bus f

12、or longer time Burst Extended Data Out: Internal counter drives address latch. Able to provide data in burst mode.Synchronous DRAM SDRAM: All of the above with clock. Adds predictability to DRAM operation DDR, DDR2, DDR3: Transfer data on both edges of the clock FB-DIMM: DIMMs connected using point

13、to point connection instead of bus. Allows more DIMMs to be incorporated in server based systemsRDRAM Low pin count20Disk Storage21Disk OrganizationPlattersA trackA sectorA cylinder(1 to 12)(5000 to 30000)(100 to 500)512 Bytes3600 to 15000 RPM22Disk OrganizationRead/write Head (10s of nanometers abo

14、ve magnetic surface)Arm23Disk Access Time Seek timeMove the arm to the desired track5ms to 12ms Rotation latency (or delay)For example, average rotation latency for a 10,000 RPM disk is 3ms (=0.5/(10,000/60) Data transfer latency (or throughput)Some tens of hundreds of MB per secondE.g., Seagate Che

15、etah 15K.6 sustained 164MB/sec Disk controller overhead Use Disk cache (or cache buffer) to exploit locality4 to 32MB todayCome with the embedded controller in the HDD24Reliability, Availability, Dependability Program faults25Reliability, Availability, Dependability Program faults Static Permanent f

16、aultsDesign flaw FDIV 500 million$Manufacturing Stuck-at-faults Process variability Dynamic faultsSoft errorsNoise-inducedWear-out26Solution Space DRAM / SRAMUse ECC (SECDED) DisksUse redundancy Users backup Disk arrays27RAID Reliability and Performance consideration Redundant Array of Inexpensive D

17、isks Combine multiple small, inexpensive disk drives Break arrays into “reliability groups” Data are divided and replicated across multiple disk drives RAID-0 to RAID-5 Hardware RAIDDedicated HW controller Software RAIDImplemented in the OS28Basic Principles Data mirroring Data striping Error correc

18、tion code29RAID-1Mirrored disksMost expensive (100% overhead)Every write to disk also writes to the check diskCan improve read/seek performance with sufficient number of controllers A4A3A2A1A0A4A3A2A1A0Disk 0(Data Disk)Disk 1(Check Disk)30RAID-10 Combine data striping atop of RAID-1B5B2A3A0B5B2A3A0D

19、ata Disk 0Data Disk 1C0B3B0A1Data Disk 2C0B3B0A1Data Disk 3B4B1A2Data Disk 4B4B1A2Data Disk 531RAID-2Bit-interleaving stripingUse Hamming CodeHamming Code to generate and store ECC on check disks (e.g., Hamming(7,4)Hamming(7,4) Space: 4 data disks need 3 check disks (75%), 10 data disks need 4 check

20、 disks (40% overhead), 25 data disks need 5 check disks (20%) CPU needs more compute power to generate Hamming code than parityComplex controllerNotNot really used today!D0C0B0A0D1C1B1A1Data Disk 0Data Disk 1D2C2B2A2Data Disk 2D3C3B3A3Data Disk 3dECC0cECC0bECC0aECC0Check Disk 0dECC1cECC1bECC1aECC1Ch

21、eckDisk 1dECC2cECC2bECC2aECC2CheckDisk 232RAID-3 Byte-level striping Use XOR parityXOR parity to generate and store parity code on the check disk At least 3 disks: 2 data disks + 1 check diskD0C0B0A0D1C1B1A1Data Disk 0Data Disk 1D2C2B2A2Data Disk 2D3C3B3A3Data Disk 3ECCdECCcECCbECCaCheck Disk 0OneTr

22、ansferUnit33RAID-4Block-level stripingKeep each individual accessed unit in one disk Do not access all disks for (small) transfers Improved parallelism Use XOR parityXOR parity to generate and store parity code on the check diskCheck info is calculated over a piece of each transfer unitSmall read one read on one diskSmall write two reads and two writes (data and check disks) New parity = (old data new data) old parity No need to read B0, C0, and D0 when read-modify-write A0Write is the bottlenecks as all writes access the check diskA3A2A1A0B3B