自动洗衣机控制器ddpp课程设计概要

1、电子科技大学数字设计原理与实践课程设计报题目：自动洗衣机控制器姓名：魏玉峰学号： 2012171010009一、任务与要求设计内容： 1）进行需求分析，确定总体框架；2 ）画出逻辑电路图；3 ）对设计电路进行仿真； 设计要求：假设自动洗衣机的定时操作顺序是，洗衣 10min，排水 2min，脱水 3min，然后停止。设计出这个自动洗衣机的控制器。设计提示：本设计有 4 个状态，分别为初始状、洗衣系统、排水系统、和脱水状 态。当有复位信号时，系统进入循环控制状态，依次执行操作，可从信号灯观察 到所处状态。二、设计思路的介绍分析：洗衣机开机后， 自动进入循环状态， 分别进行洗衣 10min，排水

2、2min， 脱水 3min 的操作，然后回到待机状态。任意期间输入复位信号都会重新开始进 入循环控制状态。 LED指示灯与当前操作对应，处于发光状态。由以上要求可知， 所有状态共 4 种，分别为初始状态、 洗衣状态、 排水状态、 和脱水状态，即用 1个 74163计时器，输出的状态与上面一一对应， 具体见下表：0000待机0001洗衣状态0010洗衣状态0011洗衣状态0100洗衣状态0101洗衣状态0110洗衣状态0111洗衣状态1000洗衣状态1001洗衣状态1010洗衣状态1011排水状态1100排水状态1101脱水状态1110脱水状态1111脱水状态故可根据上表分别选择输出时的 741

3、63 对应输出接口三、总体方案的选择经过多次选择与比较最终选择 74163,7400 来完成电路实现计时功能。将时 钟信号设为 1/60hz，即每分钟一个上升沿。电路中采用 16个 4输入与非门， 1 个 12 输入与非门， 1 个 2 输入与非门， 1 个 3 输入与非门。 把每一个 4 输入与非 门的四个角分别于 74163的 Qd、Qc、Qb、Qa相连，而每一个 4输入与非门分 别对应一个 74163 的输出状态。当所输出状态对应了洗衣机状态时， 总输出状态 将产生变化，从而进行当前操作，具体电路图设计如下：Clk 为时钟信号 1/60hzInput 为开关按钮Clr 为复位按钮Stan

4、dby代表当前为待机状态Washing代表当前为洗衣状态Drainage代表当前为排水状态Dehydration 代表当前为洗衣状态四、Verilog HDL 代码module try3(wireSYNTHESIZED_WIRE_39;clk,wireSYNTHESIZED_WIRE_42;input,wireSYNTHESIZED_WIRE_43;clr,wireSYNTHESIZED_WIRE_44;Standby,wireSYNTHESIZED_WIRE_51;Washing,wireSYNTHESIZED_WIRE_53;Drainage,wireSYNTHESIZED_WIRE_78

5、;DehydrationwireSYNTHESIZED_WIRE_84;);wireSYNTHESIZED_WIRE_85;wireSYNTHESIZED_WIRE_86;wireSYNTHESIZED_WIRE_88;inputclk;wireSYNTHESIZED_WIRE_90;inputinput;wireSYNTHESIZED_WIRE_91;inputclr;wireSYNTHESIZED_WIRE_118;outputStandby;wireSYNTHESIZED_WIRE_95;outputWashing;wireSYNTHESIZED_WIRE_96;outputDraina

6、ge;wireSYNTHESIZED_WIRE_97;outputDehydration;wireSYNTHESIZED_WIRE_98;wireSYNTHESIZED_WIRE_99;wireSYNTHESIZED_WIRE_114;wireSYNTHESIZED_WIRE_100;wireSYNTHESIZED_WIRE_115;wireSYNTHESIZED_WIRE_101;wireSYNTHESIZED_WIRE_2;wireSYNTHESIZED_WIRE_102;wireSYNTHESIZED_WIRE_116;wireSYNTHESIZED_WIRE_103;wireSYNTH

7、ESIZED_WIRE_117;wireSYNTHESIZED_WIRE_104;wireSYNTHESIZED_WIRE_5;wireSYNTHESIZED_WIRE_105;wireSYNTHESIZED_WIRE_6;wireSYNTHESIZED_WIRE_106;wireSYNTHESIZED_WIRE_7;wireSYNTHESIZED_WIRE_107;wireSYNTHESIZED_WIRE_8;wireSYNTHESIZED_WIRE_108;wireSYNTHESIZED_WIRE_9;wireSYNTHESIZED_WIRE_112;wireSYNTHESIZED_WIR

8、E_10;wireSYNTHESIZED_WIRE_113;wireSYNTHESIZED_WIRE_12;74163 b2v_inst(wireSYNTHESIZED_WIRE_13;wireSYNTHESIZED_WIRE_16;wireSYNTHESIZED_WIRE_17;wireSYNTHESIZED_WIRE_18;.ENT(input),wireSYNTHESIZED_WIRE_23;wireSYNTHESIZED_WIRE_24;.CLRN(clr),wireSYNTHESIZED_WIRE_25;.CLK(clk),wireSYNTHESIZED_WIRE_34;.ENP(i

9、nput),wireSYNTHESIZED_WIRE_36;.LDN(input),wireSYNTHESIZED_WIRE_38;.QA(SYNTHESIZED_WIRE_115),.QB(SYNTHESIZED_WIRE_116),.QC(SYNTHESIZED_WIRE_117),.QD(SYNTHESIZED_WIRE_114);assign SYNTHESIZED_WIRE_105 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_116

10、);assign SYNTHESIZED_WIRE_2 = SYNTHESIZED_WIRE_117;assign SYNTHESIZED_WIRE_113 = (SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6 & SYNTHESIZED_WIRE_7 & SYNTHESIZED_WIRE_8);assign SYNTHESIZED_WIRE_100 = (SYNTHESIZED_WIRE_9 & SYNTHESIZED_WIRE_10 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WI

11、RE_12);assign SYNTHESIZED_WIRE_102 = (SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_16);assign SYNTHESIZED_WIRE_101 = (SYNTHESIZED_WIRE_17 & SYNTHESIZED_WIRE_18 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assign SYNTHESIZED_WIRE_118 =

12、 (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_23 & SYNTHESIZED_WIRE_24);assign SYNTHESIZED_WIRE_103 = (SYNTHESIZED_WIRE_25 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assign SYNTHESIZED_WIRE_108 = (SYNTHESIZED_WIRE_114 & SYNTHE

13、SIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assign SYNTHESIZED_WIRE_104 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_36);assign SYNTHESIZED_WIRE_96 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_38 & SYNTHESIZED_WIR

14、E_39 & SYNTHESIZED_WIRE_116);assign SYNTHESIZED_WIRE_95 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44);assign SYNTHESIZED_WIRE_7 = SYNTHESIZED_WIRE_117;assign SYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_116;assign SYNTHESIZED_WIRE_6 = SYNTHESIZED

15、_WIRE_115;assign SYNTHESIZED_WIRE_90 = SYNTHESIZED_WIRE_117;assign SYNTHESIZED_WIRE_91 = SYNTHESIZED_WIRE_116;assign SYNTHESIZED_WIRE_97 = (SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_116);assign SYNTHESIZED_WIRE_88 = SYNTHESIZED_WIRE_114;assign SY

16、NTHESIZED_WIRE_84 = SYNTHESIZED_WIRE_114;assign SYNTHESIZED_WIRE_86 = SYNTHESIZED_WIRE_117;assign SYNTHESIZED_WIRE_85 = SYNTHESIZED_WIRE_115;assign SYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_114;assign SYNTHESIZED_WIRE_53 = SYNTHESIZED_WIRE_117;assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_114;assign SYN

17、THESIZED_WIRE_12 = SYNTHESIZED_WIRE_116;assign SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_115;assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_114;assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_116;assign SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_114;assign SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_115;assign SYN

18、THESIZED_WIRE_25 = SYNTHESIZED_WIRE_114;assign SYNTHESIZED_WIRE_43 = SYNTHESIZED_WIRE_117;assign SYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_115;assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_117;assign SYNTHESIZED_WIRE_112 = SYNTHESIZED_WIRE_116;assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_116;assign SY

19、NTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_117;assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_115;assign SYNTHESIZED_WIRE_107 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_78 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_116;assign SYNTHESIZED_WIRE_34

20、 = SYNTHESIZED_WIRE_115;assign SYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_115;assign SYNTHESIZED_WIRE_98 = (SYNTHESIZED_WIRE_84 & SYNTHESIZED_WIRE_85 & SYNTHESIZED_WIRE_86 & SYNTHESIZED_WIRE_116);assign SYNTHESIZED_WIRE_99 = (SYNTHESIZED_WIRE_88 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_W

21、IRE_90 & SYNTHESIZED_WIRE_91);assign Washing = (SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_95 & SYNTHESIZED_WIRE_96 & SYNTHESIZED_WIRE_97 & SYNTHESIZED_WIRE_98 & SYNTHESIZED_WIRE_99 & SYNTHESIZED_WIRE_100 & SYNTHESIZED_WIRE_101 & SYNTHESIZED_WIRE_102 & SYNTHESIZED_WIRE_103);assign Drainage = (SYNTHESIZED_WIRE_104 & SYNTHESIZED_WIRE_105)