system-bus-nocPPT优秀课件

1、1System Busses / Networks-on-ChipEECE 579 - Advanced Topics in VLSI DesignSpring 2009Brad Quinton2OutlineSimple systems bussesOverviewAMBA APBAdvantages/Limitations Complex systems bussesOverviewAMBA AHBAdvantages/LimitationsNetworks-on-Chip (NoC)OverviewAMBA AXIResearch Topics: Topology, Protocol,

2、VLSI Implementation.Review: “A Generic Architecture for On-Chip Packet-Switched Interconnections”3Bluetooth “Platform” SoCMacintosh PICTimage form atis not supportedProcessorMemory ControllerApplication Specific LogicLow-speed I/O and Support LogicSystem Bus / Hardware I/F4Simple System Busses5Simpl

3、e System BussesThe primary goal of a simple system bus is to allow software (running on a processor) to communicate with other hardware in the SoCThere are many different implementation . but they are all very similar6Embedded Processor I/ORISC-based embedded processors communicate with external har

4、dware using two simple instructions:7Embedded Processor I/ORISC-based embedded processors communicate with external hardware using two simple instructions:Load Operation: Copies a word of data from a specific address to a local registerStore Operation: Copies a word of data from a local register to

5、a specific address8Embedded Processor I/ORISC-based embedded processors communicate with external hardware using two simple instructions:Load Operation: Copies a word of data from a specific address to a local registerStore Operation: Copies a word of data from a local register to a specific address

6、The simple system bus is just a direct extension of this model9Embedded Processor I/O10Embedded Processor I/OSoftware sets up the register with the address and data .11Embedded Processor I/OSoftware sets up the register with the address and data .Blocks decode addresses to see if they are the target

7、s.12Embedded Processor I/OSoftware sets up the register with the address and data .Blocks decode addresses to see if they are the targets.Data transferred between register and hardware13AMBA SpecificationAMBA: Advanced Microcontroller Bus ArchitectureCreated by ARM to enable standardized interfaces

8、to their embedded processorsActually three standards: APB, AHB, and AXIVery commonly used for commercial IP cores14AMBA SpecificationAMBA: Advanced Microcontroller Bus ArchitectureCreated by ARM to enable standardized interfaces to their embedded processorsActually three standards: APB, AHB, and AXI

9、Very commonly used for commercial IP coresSimple Bus15AMBA SpecificationAMBA: Advanced Microcontroller Bus ArchitectureCreated by ARM to enable standardized interfaces to their embedded processorsActually three standards: APB, AHB, and AXIVery commonly used for commercial IP coresSimple BusComplex B

10、us16AMBA SpecificationAMBA: Advanced Microcontroller Bus ArchitectureCreated by ARM to enable standardized interfaces to their embedded processorsActually three standards: APB, AHB, and AXIVery commonly used for commercial IP coresNoCSimple BusComplex Bus17AMBA APB: Read OperationMacintosh PICTimage

11、 formatis not supported18AMBA APB: Read OperationMacintosh PICTimage formatis not supportedTarget Address19AMBA APB: Read OperationMacintosh PICTimage formatis not supportedTarget AddressTransaction Type20AMBA APB: Read OperationMacintosh PICTimage formatis not supportedTarget AddressTransaction Typ

12、eAddress Decode21AMBA APB: Read OperationMacintosh PICTimage formatis not supportedTarget AddressTransaction TypeAddress DecodeOptional (for asynchronous implementations.)22AMBA APB: Read OperationMacintosh PICTimage formatis not supportedTarget AddressTransaction TypeAddress DecodeOptional (for asy

13、nchronous implementations.)Read Data23AMBA APB: Write OperationMacintosh PICTimage formatis not supported24AMBA APB: Write OperationMacintosh PICTimage formatis not supportedCommon Signals Between Read and Write25AMBA APB: Write OperationMacintosh PICTimage formatis not supportedWrite DataCommon Sig

14、nals Between Read and Write26Remember Our Case Study- data width:16 bits- address width: 16 bits- read cycle time: 50 ns- write cycle time: 50 ns Simple generic processor interface:27- data width:16 bits- address width: 16 bits- read cycle time: 50 ns- write cycle time: 50 ns Simple generic processo

15、r interface:System busRemember Our Case Study28Simple Bus AdvantagesSimple to implementEasy to understandSimple programming modelEasy to add new hardware blocksMinimal hardware requirements (most of the signals are shared)29Simple Bus LimitationsSingle Master - limits parallelismScalability - perfor

16、mance suffers as bus is loaded.Single outstanding request - poor throughput and multi-threading performance bottleneck30Case Study: Single MasterImagine a new partition: APS Bit Error Monitor communicates directly with SwitchSimple bus doesnt work.31Case Study: Single MasterNo PathImagine a new part

17、ition: APS Bit Error Monitor communicates directly with SwitchSimple bus doesnt work.32Case Study: Single MasterNo PathThis can make software the bottleneck in the system.Imagine a new partition: APS Bit Error Monitor communicates directly with SwitchSimple bus doesnt work.33Single Master SummaryA b

18、us that is limited to a single master:Makes inter-block communication inefficientLimits parallelism between hardware and softwareIncreases reliance on interruptsCreates software performance bottlenecksIs not compatible with multiple processors 34Scalability35ScalabilityBlocks are functionally easy t

19、o add, but. 36ScalabilityEach new block increases the delay on the address and data Blocks are functionally easy to add, but. 37Scalability SummarySimple busses are not scaleable because:The address and data “fan-out” to each targetAdding a new block increases the load on the bus Increased fanout +

20、greater load = reduce performance38Single Outstanding RequestMacintosh PICTimage formatis not supported39Single Outstanding RequestMacintosh PICTimage formatis not supportedProcessor is stalled waiting for response.40Single Outstanding RequestMacintosh PICTimage formatis not supportedProcessor is st

21、alled waiting for response.best-case backpressuredifficult to provide performance guarantees.Still potentially a bandwidth bottleneckStill doesnt scale well when blocks are addedMultiple outstanding transactions not handled well - no ordering information64Networks-on-Chip (NoCs)65Networks-on-ChipIt

22、is clear that even with significant design effort the bus-style interconnect is not going to sufficient for large SoCs:the physical implementation does not scale: bus fanout, loading, arbitration depth all reduce operating frequencythe available bandwidth does not scale: the single bus must be share

23、d by all masters and slaves66Networks-on-ChipIt is clear that even with significant design effort the bus-style interconnect is not going to sufficient for large SoCs:the physical implementation does not scale: bus fanout, loading, arbitration depth all reduce operating frequencythe available bandwi

24、dth does not scale: the single bus must be shared by all masters and slavesLets start again: Leverage research from data networking67What do we want?The SoCs of the future will:have 100s of hardware blocks,have billions of transistors, have multiple processors,have large wire-to-gate delay ratios,ha

25、ndle large amounts of high-speed data,need to support “plug-and-play” IP blocksOur NoC needs to be ready for these SoCs.68The Ideal NetworkWhat would the ideal network look like?:Low area overheadSimple implementationHigh-speed operationLow-latencyHigh-bandwidthOperate at a constant frequency even w

26、ith additional blocksIncrease available bandwidth as blocks are addedProvide performance guaranteesHave a “universal” interface69The Ideal NetworkWhat would the ideal network look like?:Low area overheadSimple implementationHigh-speed operationLow-latencyHigh-bandwidthOperate at a constant frequency

27、 even with additional blocksIncrease available bandwidth as blocks are addedProvide performance guaranteesHave a “universal” interfaceThese are competing requirements: Design a network that is the “best” fit.70What do we need to decide?Network InterfaceNetwork Protocol / Transaction FormatNetwork To

28、pologyVLSI Implementation71Network InterfaceWe want our network to be “plug-and-play” so industry standardization is keyHowever the standard be universal enough to address many different needsAMBA AXI is an example of an attempt at this72AMBA AXIARM added the AXI specification to Version 3.0 of the

29、AMBA standardNew approach: define the interface and leave the interconnect up to the designersGood plan since a specific bus implementation is no longer requiredIt is possible to use AXI to build many different NoCs73AMBA AXIInterface divided into 5 channels:Write AddressWrite DataWrite ResponseRead

30、 AddressRead Data/ResponseEach channel is independent and use two-way flow control74AMBA AXI Read ChannelsM a c i n t o s h P I C Ti m a g e f o r m a ti s n o t s u p p o r t e d75AMBA AXI Read ChannelsM a c i n t o s h P I C Ti m a g e f o r m a ti s n o t s u p p o r t e dIndependent76AMBA AXI Re

31、ad ChannelsM a c i n t o s h P I C Ti m a g e f o r m a ti s n o t s u p p o r t e dGive me some dataIndependent77AMBA AXI Read ChannelsM a c i n t o s h P I C Ti m a g e f o r m a ti s n o t s u p p o r t e dGive me some dataHere you goIndependent78AMBA AXI Read ChannelsM a c i n t o s h P I C Ti m

32、 a g e f o r m a ti s n o t s u p p o r t e dGive me some dataHere you goIndependentchannels synchronized with ID # or “tags”79AMBA AXI Write ChannelsM acintosh P IC Tim age form atis not supported80AMBA AXI Write ChannelsM acintosh P IC Tim age form atis not supportedIndependentIndependent81AMBA AX

33、I Write ChannelsM acintosh P IC Tim age form atis not supportedIm sending data. Please store it.IndependentIndependent82AMBA AXI Write ChannelsM acintosh P IC Tim age form atis not supportedIm sending data. Please store it.Here is the data.IndependentIndependent83AMBA AXI Write ChannelsM acintosh P

34、IC Tim age form atis not supportedIm sending data. Please store it.Here is the data.I received that data correctly.IndependentIndependent84AMBA AXI Write ChannelsM acintosh P IC Tim age form atis not supportedIm sending data. Please store it.Here is the data.I received that data correctly.Independen

35、tIndependentchannels synchronized with ID # or “tags”85AMBA AXI Flow-ControlInformation moves only when:Source is Valid, andDestination is ReadyOn each channel the master or slave can limit the flowVery flexibleMa c i n t o s h P I CTi ma g e f o r ma ti s n o t s u p p o r t e dM a c i n t o s h P

36、I C Ti m a g e f o r m a ti s n o t s u p p o r t e dM a c i n t o s h P I C Ti ma g e f o r ma ti s n o t s u p p o r t e d86M a c i n t o s h P I C Ti ma g e f o r ma ti s n o t s u p p o r t e dM a c i n t o s h P I C Ti m a g e f o r m a ti s n o t s u p p o r t e dMa c i n t o s h P I CTi ma g

37、e f o r ma ti s n o t s u p p o r t e dAMBA AXI Flow-ControlInformation moves only when:Source is Valid, andDestination is ReadyOn each channel the master or slave can limit the flowVery flexibleTransfer87AMBA AXI Flow-ControlThis definition of very independent, fully flow-controlled channels is ver

38、y usefulHowever, there is a potential problem: 88AMBA AXI Flow-ControlThis definition of very independent, fully flow-controlled channels is very usefulHowever, there is a potential problem: DEADLOCK89AMBA AXI Flow-ControlThis definition of very independent, fully flow-controlled channels is very us

39、efulHowever, there is a potential problem: DEADLOCKOn a write transaction the master must not wait for AWREADY before asserting WVALID90AMBA AXI Read Ma c i n t o s h P I C Ti ma g e f o r ma ti s n o t s u p p o r t e d91AMBA AXI Read Ma c i n t o s h P I C Ti ma g e f o r ma ti s n o t s u p p o r

40、 t e dRead Address ChannelRead Data Channel92AMBA AXI WriteM a c in to s h P IC Tim a g e fo r m a tis n o t s u p p o r te d93AMBA AXI WriteM a c in to s h P IC Tim a g e fo r m a tis n o t s u p p o r te dWrite Address ChannelWrite Response ChannelWrite Data Channel94A True Interface Specification

41、Because of the channel independence and the two-way flow-control the interface does not dictate the network protocol, transaction format, network topology, or VLSI implementationFor example:if you want to build a packet-based network, you can “backpressure” the data channel while you build the packe

42、t header from the address channel information,you can use store-and-forward, or cut-through, etc.95Network Protocol / Transaction FormatThere are many choice for network protocols and transactions formats:circuit-switched : plan and provision a connection before communication startspacket-switched :

43、 issues packets which compete for network resourceshybrids: schedule connectivity (dynamic or static)96Network Protocol / Transaction FormatThere are many choice for network protocols and transactions formats:circuit-switched : plan and provision a connection before communication startspacket-switched : issues packets which compete for network resourceshybrids: schedule connectivity (dynamic or static)There is still lots of research here.97Network TopologyHow should your network elements be interconnected:Ful