学习笔记fpga设计电子时钟(12864显示)

1、fpga 设计电子时钟（ 12864 显示）设计心得：1，进行分块设计，类似调用函数，脉冲使能2，充分了解 fpga 的并行特性（ c 程序的串行特性，不能并行处理，线性：只有完成了当前 任务，才能进行下一个任务）设计问题：1，似乎读有问题，在 char_LR=1 时，写的数据为汉字（程序中时间没有更改，主要为了调试看波形） 实际板子验证时，将 LCD_clk 模块中的分频调为 50 到 100kHz 左右整体架构非忙应答1，液晶上电初始化2，清屏功能模块1，采用绘图模式2，一次一个汉字3，位置，编码编号1，采用 CDRAM 模式2，一次一个字符3，位置1，采用绘图模式 2，大小可变（库编码内

2、存不变） 3，位置，长宽液晶初始化时序parameter IdleBasic_comDisp_set=8b0000_0001,=8b0000_0010,=8b0000_0100,DDRAM_clear =8b0000_1000,Wait_clear =8b0001_0000,Point_set =8b0010_0000,Show_on =8b0100_0000,/basic instruction:0x30 /set show curse bling /colunm address XStop=8b1000_0000;写字符的时序由于字符属于半宽字形，且DDRAM 形式下，每行只有 8 个地址

3、，而字符可以写 16 个，因此用下面三个来表示写的地址：input 1:0Y,/row 0-3input 2:0X,/clunm 0-7inputLR, /0/1因此当 LR=0 时，直接写地址，然后写一个字符编码即可LR=1时，先写地址，读出高位数据，然后写入两个字节（读出的数据，要写的数据）parameter Idle=8b0000_0001,DDRAM=8b0000_0010,/drawing modeW_addr=8b0000_0100,/row address YDummy=8b0000_1000,/ not really readingR_data=8b0001_0000,/rea

4、ding high byte dataW0_data=8b0010_0000,W1_data=8b0100_0000,Stop=8b1000_0000;# t1:0 t2:2305, T:10,n_init:38# t1:2305 t2:2665, T:10,n_char:6# t1:2665 t2:3265, T:10,n_char:10完成了上述工作，就可以设计一个简单的电子时钟，其要求如下： 在屏幕上显示时间 00：00： 00 要动态走（主要就是控制脉冲信号的产生）设计思路：1，按下复位键，系统复位，时间变为00：00： 002，每一秒中时分秒数据更改3，一秒钟时间到，产生 8 个字符

5、写的脉冲， LCD更新数据显示00:00:0100:01:591 代码/*sign.v/creat the control signclock h:m:s*/module sign(/module LED(input lcd_clk, /100kHz input sys_rst, output reg lcd_char_en, output reg lcd_init_en, output reg 7:0char_data, output reg 2:0char_X, output reg 1:0char_Y , output reg char_LR);parameter T_w_char =

6、5,T_lcd_init = 40;reg 47:0 time_out;/* 1s */reg 16:0 cnt_s;reg 5:0 cnt0_clk;reg 3:0 cnt1_clk;reg 2:0 cnt_char;reg 5:0 sec,min;reg 4:0 hour;reg flag_s,flag_init;always (posedge lcd_clk or negedge sys_rst) begin /100kHz if(!sys_rst)begin cnt_s =0; cnt0_clk=0; cnt1_clk=0; cnt_char=0; sec =0; min =0; ho

7、ur =0; flag_s =0; flag_init =1b1; char_Y = 2b10;endelsebeginif(cnt_s = (40-1)begincnt_s =0; flag_s=1b1; data_deal; /task endelsecnt_s =cnt_s+1b1;if(flag_init)begincnt0_clk = cnt0_clk +1b1; case(cnt0_clk)1: beginlcd_init_en =1b0; end2: beginlcd_init_en =1b1; end3: beginlcd_init_en =1b1; end4: beginlc

8、d_init_en =1b0; endT_lcd_init: begincnt0_clk =0;enddefault: lcd_init_en =0; endcaseendelse if(flag_s) begincnt1_clk = cnt1_clk +1b1; case(cnt1_clk)1 :beginlcd_char_en =1b0; end2 :beginlcd_char_en =1b1; end3 :beginlcd_char_en =1b1; end4 :beginlcd_char_en =1b0; endT_w_char:beginif(cnt_char = 3b111)beg

9、in cnt_char=0; flag_s =0; end elsecnt_char =cnt_char+1b1;cnt1_clk =0;enddefault: lcd_char_en =0;endcase case(cnt_char)/2 3 4 5 0 : begin char_X =3b000; char_LR =0; char_data =time_out47:40;end /x0:00:001 : begin char_X =3b001; char_LR =0; char_data =time_out39:32; end / 0x:00:002 : begin char_X =3b0

10、10; char_LR =0; char_data =8h3a; end /: ascii 0583 : begin char_X =3b011; char_LR =0; char_data =time_out31:24; end / 00:x0:004 : begin char_X =3b100; char_LR =0; char_data =time_out23:16; end / 00:0x:005 : begin char_X =3b101; char_LR =0; char_data =8h3a; end /: ascii0586 : begin char_X =3b110; cha

11、r_LR =0; char_data =time_out15: 8; end/ 00:00:x07 : begin char_X =3b111; char_LR =0; char_data =time_out7 : 0; endendcaseendend end task data_deal;beginif(sec = 59)if(min =59)if(hour = 23)begin hour=0;min =0;sec =0; end elsebegin hour=hour + 1b1; min =0; sec=0; end elsebegin min = min+1b1; sec =0; e

12、ndelsesec = sec +1b1;time_out47:40 = 8h30+(hour/10);time_out39:32 = 8h30+(hour%10);time_out31:24 = 8h30+(min /10);time_out23:16 = 8h30+(min %10);time_out15: 8 = 8h30+(sec /10); time_out 7: 0 = 8h30+(sec %10);endendtaskendmodule2 代码module LCD_init(/module LED(input lcd_clk,input sys_clk,input lcd_en,

13、/1 is activedoutput reg LCD_RS, output reg LCD_RW, output reg LCD_EN,inout 7:0 LCD_DATA,output reg ACK );reg flag;reg 7:0 lcd_data;reg 7:0 State;reg link_rs;reg link_data;parameter Idle =8b0000_0001,Basic_com =8b0000_0010, /basic instruction:0x30Disp_set =8b0000_0100, /set show curse blingDDRAM_clea

14、r =8b0000_1000, /colunm address XWait_clear =8b0001_0000,Point_set =8b0010_0000,Show_on =8b0100_0000,Stop =8b1000_0000;reg 9:0 cnt; /16*2*32=210 byte(8bits)/* LCD_RW LCD_DATA*/assign LCD_DATA = link_data ? lcd_data: 8hzz;/* LCD_RW LCD_EN */always (posedge sys_clk) beginif(flag)beginLCD_RW =0;LCD_EN

15、= lcd_clk;endelsebeginLCD_RW =1bz;LCD_EN =1bz;endend/* LCD_RS */always (posedge lcd_clk) beginif(link_rs)LCD_RS =1b0;elseLCD_RS =1bz;end/*-Main state transter-*/always (posedge lcd_clk) begincase (State)Idle : beginif(lcd_en)begin link_rs=1; State = Basic_com; endelseState = Idle;ACK =0; flag =1b0;

16、lcd_data = 8hzz;cnt = 0;end Basic_com : beginflag =1b1; link_data =1b1; cnt = cnt +1b1;if(cnt = 1)State = Disp_set;elseState = Basic_com; lcd_data = 8h30;endDisp_set : beginState = DDRAM_clear; lcd_data = 8h0c; /show curse blink is off endDDRAM_clear : beginState = Wait_clear; lcd_data = 8h01;endWai

17、t_clear : begin cnt =cnt +1b1; link_data = 1b0; flag =0; lcd_data = 8hzz; if(cnt = 30)State = Point_set; elseState = Wait_clear;endPoint_set : beginflag =1b1; link_data =1b1;State = Show_on;lcd_data = 8h06; /point +1 automatically,screen move off endShow_on : beginState = Stop; lcd_data = 8h0c;endSt

18、op : beginState = Idle; flag =1b0; link_data =1b0;ACK =1b1; lcd_data = 8hzz; cnt = 0; link_rs =0;enddefault: begin ACK =0;State = Idle;end endcase end endmodule3 代码/module LCD_top( module LED(inputsys_clk,inputsys_rst,outputLCD_RS,outputLCD_RW,outputLCD_EN,inout7:0 LCD_DATA,output BUSY);wire 7:0 cha

19、r_data;wire 2:0 char_X;wire 1:0 char_Y; sign singb(.lcd_clk (lcd_clk), /100kHz .sys_rst (sys_rst), .lcd_char_en(lcd_char_en), .lcd_init_en(lcd_init_en), .char_data (char_data), .char_X(char_X),.char_Y(char_Y),.char_LR (char_LR) );LCD_init lcd_init(.lcd_clk (lcd_clk),.sys_clk (sys_clk),.lcd_en(lcd_in

20、it_en),/1 is actived.LCD_RS(LCD_RS),.LCD_RW(LCD_RW),.LCD_EN(LCD_EN),.LCD_DATA (LCD_DATA), .ACK (init_ack);LCD_charac a(.lcd_clk (lcd_clk),.sys_clk (sys_clk),.lcd_en (lcd_char_en),/1 is actived.Y(char_Y),/row 0-3.X(char_X),/clunm 0-7.LR(char_LR),/0/1.data_disp(char_data),.LCD_RS(LCD_RS),.LCD_RW(LCD_R

21、W),.LCD_EN(LCD_EN),.LCD_DATA (LCD_DATA),.ACK (init_ack) );LCD_clk clk1(.sys_clk (sys_clk), .lcd_clk (lcd_clk);endmodule4 代码module LCD_clk( /module LED(input sys_clk, output reg lcd_clk );/*-creat the 25kHz clock-*/ reg 11:0 lcd_cnt;always (posedge sys_clk) begin if(lcd_cnt = 2)/100kHzbeginlcd_cnt =0

22、; lcd_clk = lcd_clk; endelselcd_cnt = lcd_cnt +1b1; end initial begin lcd_clk =0; lcd_cnt =0; end endmodule5 代码/* to display character */ module LCD_charac(/module LED(input lcd_clk,input sys_clk,input lcd_en,/1 is activedinput 1:0Y, /row 0-3input 2:0X, /clunm 0-7inputLR, /0/1input 7:0data_disp,outp

23、ut regLCD_RS,output regLCD_RW,output regLCD_EN,inout 7:0 LCD_DATA,output regACK);reg 7:0 lcd_data;reg 7:0 R_buff;reg 7:0 State;parameter Idle=8b0000_0001,DDRAM=8b0000_0010,/drawing modeW_addr=8b0000_0100,/row address YDummy=8b0000_1000,/ not really readingR_data=8b0001_0000,/reading high byte dataW0

24、_data=8b0010_0000,W1_data=8b0100_0000,Stop=8b1000_0000;reg flag,cnt;reg link_data;reg flag0;/* LCD_DATA */assign LCD_DATA = link_data ? lcd_data :8hzz;/* LCD_EN */ always (posedge sys_clk) beginif(flag = 1b1)LCD_EN = lcd_clk;elseLCD_EN =1bz;end/* LCD_RW */always (posedge lcd_clk) beginif(flag0)if(St

25、ate = Dummy | State = R_data) LCD_RW =1b1;elseLCD_RW =1b0;elseLCD_RW =1bz;end/* LCD_RS */always (posedge lcd_clk) beginif(flag0)if(State = W0_data | State = W1_data | State = Dummy | State = R_data) LCD_RS =1b1;elseLCD_RS =1b0;elseLCD_RS =1bz;end/*-Main state transter-*/ always (posedge lcd_clk) begin case (State) Idle : begin if(lcd_en)begin State = DDRAM; link_data =1; flag0=1b1; end elsebegin State = Idle;