嵌入式系统导论3硬件设计 arm

1、嵌入式系统导论,第三章,嵌入式系统硬件,Introduction to Embedded System,中南大学信息科学与工程学院,专题,1:S3c4510,及其应用系统设计,S3c4510,概述,S3c4510,系统管理,Cache,内部控制器,设计事例,专题,1:S3c4510,及其应用系统设计,一,S3C4510,概述,S3C4510B 16/32-bit RISC microcontroller,Arm Core,集成功能,8K-byte unified cache/SRAM,I2C interface,Ethernet controller,HDLC,GDMA,UART,Timers

2、,Programmable I/O ports,Interrupt controller,专题,1:S3c4510,及其应用系统设计,S3C4510,概述,Cont.,cost-effective, high-performance,应用领域,通信、控制,ARM,Advanced RISC Machines,公司、一类微处理器、一种技术,1991,年,ARM,公司成立于英国剑桥，主要,出售芯片设计技术的授权,IP,工业控制、消费类电子产品、通信系统,网络系统、无线系统等,基于,ARM,技术的微处理器应用约占据了,32,位,RISC,微处理器,75,以上的市场份额,ARM,Advanced RI

3、SC Machines,采用,RISC,架构的,ARM,微处理器一般具有如下特,点,1,体积小、低功耗、低成本、高性能,2,支持,Thumb,16,位,ARM,32,位）双指令,集，能很好的兼容,8,位,16,位器件,3,大量使用寄存器，指令执行速度更快,4,大多数数据操作都在寄存器中完成,5,寻址方式灵活简单，执行效率高,6,指令长度固定,ARM,Advanced RISC Machines,ARM,微处理器系列,ARM7,系列,ARM9,系列,ARM9E,系列,ARM10E,系列,SecurCore,系列,Intel,的,Xscale,Intel,的,StrongARM,ARM7,ARM9

4、,ARM9E,和,ARM10,为,4,个通用处理器系列，每一个系列提,供一套相对独特的性能来满足不同应用领域的需求,SecurCore,系列,专门为安全要求较高的应用而设计,ARM,Advanced RISC Machines,ARM7,系列,具有嵌入式,ICE,RT,逻辑，调试开发方便,极低的功耗，适合对功耗要求较高的应用，如便携,式产品,能够提供,0.9MIPS/MHz,的三级流水线结构,代码密度高并兼容,16,位的,Thumb,指令集,对操作系统的支持广泛，包括,Windows,CE,Linux,Palm,OS,等,指令系统与,ARM9,系列,ARM9E,系列和,ARM10E,系列兼,容

5、，便于用户的产品升级换代,主频最高可达,130MIPS,高速的运算处理能力能胜,任绝大多数的复杂应用,ARM,Advanced RISC Machines,ARM9,系列,5,级整数流水线，指令执行效率更高,提供,1.1MIPS/MHz,的哈佛结构,支持,32,位,ARM,指令集和,16,位,Thumb,指令集,支持,32,位的高速,AMBA,总线接口,全性能的,MMU,支持,Windows,CE,Linux,Palm,OS,等多种主流嵌入式操作系统,MPU,支持实时操作系统,支持数据,Cache,和指令,Cache,具有更高的指,令和数据处理能力,ARM,Advanced RISC Mach

6、ines,ARM9E,微处理器系列,支持,DSP,指令集，适合于需要高速数字信号处理的,场合,5,级整数流水线，指令执行效率更高,支持,32,位,ARM,指令集和,16,位,Thumb,指令集,支持,32,位的高速,AMBA,总线接口,支持,VFP9,浮点处理协处理器,全性能的,MMU,支持,Windows,CE,Linux,Palm,OS,等多种主流嵌入式操作系统,MPU,支持实时操作系统,支持数据,Cache,和指令,Cache,具有更高的指令和数,据处理能力,主频最高可达,300MIPS,ARM,Advanced RISC Machines,ARM10E,微处理器系列,支持,DSP,指令

7、集，适合于需要高速数字信号处理的,场合,6,级整数流水线，指令执行效率更高,支持,32,位,ARM,指令集和,16,位,Thumb,指令集,支持,32,位的高速,AMBA,总线接口,支持,VFP10,浮点处理协处理器,全性能的,MMU,支持,Windows,CE,Linux,Palm,OS,等多种主流嵌入式操作系统,支持数据,Cache,和指令,Cache,具有更高的指令和数,据处理能力,主频最高可达,400MIPS,内嵌并行读,写操作部件,ARM,Advanced RISC Machines,StrongARM,微处理器系列,Intel,StrongARM,SA-1100,处理器是采用,AR

8、M,体系结构高度集成的,32,位,RISC,微处理器,融合了,Intel,公司的设计和处理技术以及,ARM,体系结构的电源效率,采用在软件上兼容,ARMv4,体系结构、同时采,用具有,Intel,技术优点的体系结构,ARM,Advanced RISC Machines,Xscale,处理器,基于,ARMv5TE,体系结构,它支持,16,位的,Thumb,指令和,DSP,指令集,数字移动电话、个人数字助理和网络产品等,Samsung S3C4510B,简介,集成,ARM7TDMI,RISC,处理器核,合用于对价格及功耗敏感的应用,结构框图如下,Samsung S3C4510B,简介,Archit

9、ecture,Integrated system for embedded ethernet,applications,Fully 16/32-bit RISC architecture,Little/Big-Endian mode supported basically, the,internal architecture is big-endian.So, the little,endian mode only support for external memory,Efficient and powerful ARM7TDMI core,Cost-effective JTAG-based

10、 debug solution,Boundary scan,Samsung S3C4510B,简介,System Manager,8/16/32-bit external bus support for ROM/SRAM,flash memory, DRAM, and external I/O,One external bus master with bus request,acknowledge pins,Support for EDO/normal or SDRAM,Programmable access cycle (0-7 wait cycles,Four-word depth wri

11、te buffer,Cost-effective memory-to-peripheral DMA,interface,Samsung S3C4510B,简介,Unified Instruction/Data Cache,Two-way, set-associative, unified 8K-byte cache,Support for LRU (least recently used) protocol,Cache is configurable as an internal SRAM,I2C Serial Interface,Master mode operation only,Baud

12、 rate generator for serial clock generation,Samsung S3C4510B,简介,Ethernet Controller,DMA engine with burst mode,DMA Tx/Rx buffers (256 bytes Tx, 256 bytes Rx,MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes Rx,Data alignment logic,Endian translation,100/10-Mbit per second operation,Full compliance with

13、IEEE standard 802.3,MII and 7-wire 10-Mbps interface,Full-duplex mode with PAUSE feature,Samsung S3C4510B,简介,HDLCs,HDLC protocol features,Selectable CRC or No CRC mode,Automatic CRC generator preset,Baud rate generator,NRZ/NRZI/FM/Manchester data formats for Tx/Rx,Loop-back and auto-echo modes,Tx/Rx

14、 FIFOs have 8-word (8,32-bit) depth,Endian translation,Programmable interrupts,Modem interface,Up to 10 Mbps operation,2-channel DMA buffer descriptor for Tx/Rx on each HDLC,Samsung S3C4510B,简介,UARTs,Two UART (serial I/O) blocks with DMA-based or interrupt,based operation,Support for 5-bit, 6-bit, 7

15、-bit, or 8-bit serial data transmit,and receive,Programmable baud rates,1 or 2 stop bits,Odd or even parity,Break generation and detection,Parity, overrun, and framing error detection,16 clock mode,Infra-red (IR) Tx/Rx support (IrDA,Samsung S3C4510B,简介,Timers,Two programmable 32-bit timers,Interval

16、mode or toggle mode operation,Programmable I/O,18 programmable I/O ports,Pins individually configurable to input, output, or,I/O mode for dedicated signals,Samsung S3C4510B,简介,Interrupt Controller,21 interrupt sources, including 4 external interrupt,sources,Normal or fast interrupt mode (IRQ, FIQ,Pr

17、ioritized interrupt handling,Samsung S3C4510B,简介,Operating Voltage Range,3.3 V,5,Operating Temperature Range,0,C to + 70,C,Operating Frequency,Up to 50 MHz,Package Type,208-Pin QFP,Samsung S3C4510B,Samsung S3C4510B,简介,系统配置(8,JTAG(5,存储器接口,83,Ethernet(18,HDLC(9*2,UART(5*2,I,2,C(2,PIO18,INT4,DMA2*2,TIM

18、ER2,18,Samsung S3C4510B,简介,Samsung S3C4510B,简介,Samsung S3C4510B,简介,Samsung S3C4510B,简介,Samsung S3C4510B,简介,Samsung S3C4510B,简介,Samsung S3C4510B,简介,Samsung S3C4510B,编程,处理器,2,种状态,ARM,执行,32-bit, word-aligned ARM,指令,THUMB,执行,16-bit, half-word-aligned THUMB,指令,优点,根据需要优化存储,状态之间方便转换,Samsung S3C4510B,编程,存储格

19、式,byte order,Big-Endian,Msb is low addr,Addrss by MSB,Little-Endian,Lsb is low addr,Addrss by LSB,Samsung S3C4510B,编程,存储格式,byte order,0 x12,0 x78,0 x56,0 x34,Example: ADDRESS:0 x10000 DATA:0 x12345678,0 x10000 0 x10001 0 x10002 0 x10003,0 x78,0 x12,0 x34,0 x56,字节地址,大端存储模式,小端存储模式,对嵌入式系统,当直接操作硬件时,字节顺序

20、很重要,S3C4510,内部为,Big-endian,外部可以通过配置引脚选择外部数据存储方式,Samsung S3C4510B,编程,ARM7TDMI,支持,7,种操作模式,User (usr,正常操作状态,FIQ (fiq,数据传输、通道处理中断,IRQ (irq,一般中断处理,Supervisor (svc,系统保护模式,Abort mode (abt,取指出错,System (sys,超级用户模式,Undefined (und,非法指令时进入该状态,Samsung S3C4510B,编程,ARM7TDMI 31,个寄存器,31,个,32,位通用寄存器,6,个状态寄存器,Samsung

21、S3C4510B,编程,ARM7TDMI 31,个寄存器,Samsung S3C4510B,编程,ARM7TDMI,指令集,指令少，但与条件组合非常复杂,在此不详细讲解,无论使用,uClinux,还是,VxWorks,在移植过,程中仅需要很少汇编指令,Samsung S3C4510B,编程,ARM7TDMI,指令例子,设置,SYSCFG,寄存器,ldr,r0, =SYSCFG,* Cache Off, Write Buffer Off, 4K SRAM, 4K CACHE *,ldr,r1, =0 x87ffff80,str,r1, r0,Samsung S3C4510B,系统管理,总线仲裁,

22、比较简单，固定优先级,提供存储器控制信号,重点讨论,Samsung S3C4510B,系统管理,5*(ROM/SRAM/FLASH)+ 4*(DRAM/SDRAM)+ 4*(EXTIO) + 8K ISRAM+16K SPR,可以把它们定义在,64M,存储空间的任意位置,存储器映像,Samsung S3C4510B,系统管理,系统启动时存储器映像,启动时，除,CS0,外，其它均无效,CS0,接,BootRom,放置启动代码,BSP/BIOS/Boot loader,Samsung S3C4510B,系统管理,系统管理寄存器,Samsung S3C4510B,系统管理,系统配置寄存器,0,必须为

23、零,1,Cache Enable,2:Write Buffer Enable 5-4:Cache Mode(cache,与,sram,划分,15-6:Internal SRAM base pointer,表示内部,SRAM,的,A25-A16,25-16:Special register bank base pointer,表示,SPR,基地址，以,64K,为单位,30-26,产品,ID,00001 = S3C4510X (KS32C50100,11001 = S3C4510B,31:DRAM,还是,SDRAM,0 x37ffff91,含义：内部,SRAM,基地址,0 x3fe0000,SPR

24、,基地址为,0 x3ff0000,Samsung S3C4510B,系统管理,时钟控制寄存器,15:0 Clock diving value,If all bits are 0, non-divided clock is used. Only one bit can,be set in CLKCON15:0. That is, the clock diving value is,defined as 1,2,4,8,16,.Internal system clock, fMCLK,fICLK/(CLKCON+1,16 ROM bank 5 wait enable,17 ROM bank 5 a

25、ddress/data bus MUX enable,19:18 MUX bus Address (tAC,31 Test bit,This bit should be always 0,Samsung S3C4510B,系统管理,系统时钟,Note:CLKSEL=1,外部时钟,Samsung S3C4510B,系统管理,EXTERNAL I/O ACCESS CONTROL,REGISTERS (EXTACON0/1,2,个,32bit,寄存器,设置,4,个,EXTIO banks,每个,bank,设置,4,个时间,tCOSx :Chip selection set-up time on n

26、OE,tACSx: Address set-up time before nECS,tCOHx:Chip selection hold time on nOE,tACCx:Access cycles (nOE low time,Samsung S3C4510B,系统管理,EXTERNAL I/O ACCESS CONTROL,REGISTERS (EXTACON0/1,tACS = 0 (0 cycle) tCOS = 0 (0 cycle,tACC = 4 (5 cycles) tCOH = 0 (0 cycle,Samsung S3C4510B,系统管理,DATA BUS WIDTH RE

27、GISTER,EXTDBWTH,DSRx:ROM/SRAM/FLASH,DSDx:DRAM/SDRAM,DSXx:EXTIO,B0SIZE1:0 = , 8 bits,B0SIZE1:0 = , 16 bits,B0SIZE1:0 = , 32 bits,注意,启动时,DSR0,由,B0SIZE,确定,Samsung S3C4510B,系统管理,ROM/SRAM/FLASH CONTROL,REGISTERS (ROMCON,Samsung S3C4510B,系统管理,ROM/SRAM/FLASH CONTROL,REGISTERS (ROMCON,1:0 Page mode configur

28、ation (PMC,00 = Normal ROM 01 = 4-word page,10 = 8-word page 11 = 16-word page,3:2 Page address access time (tPA,00 = 5 cycles 01 = 2 cycles,10 = 3 cycles 11 = 4 cycles,6:4 Programmable access cycle (tACC,000 = Disable bank 001 = 2 cycles,010 = 3 cycle 011 = 4 cycles,110 = 7 cycle 111 = Reserved,19:

29、10 ROM/SRAM/Flash bank # base pointer,base pointer 16,29:20 ROM/SRAM/FLASH bank # next pointer,This value is the current bank end address 16 + 1,Samsung S3C4510B,系统管理,ROM/SRAM/FLASH CONTROL,REGISTERS (ROMCON,Normal,tACC = 4 (5 cycles,Samsung S3C4510B,系统管理,ROM/SRAM/FLASH CONTROL,REGISTERS (ROMCON,tAC

30、C = 2 (3 cycles) tPA = 1 (2 cycles,PMC = 1 (4 word page,Samsung S3C4510B,系统管理,DRAM CONTROL REGISTERS,0 EDO mode (EDO,0 = Normal 1 = EDO DRAM,2:1 CAS strobe time (tCS) 3:3 CAS pre-charge time (tCP) 6:4 Reserved,7 RAS to CAS delay (tRC or tRCD,0 = 1 cycle 1 = 2 cycles,9:8 RAS pre-charge time (tRP,00 =

31、 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles,19:10 DRAM bank # base pointer,base pointer 16,29:20 DRAM bank # next pointer,current bank end address 16 + 1,31:30 Number of column address bits in DRAM bank # (CAN,00 = 8 bits 01 = 9 bits,10 = 10 bits 11 = 11 bits,Samsung S3C4510B,系统管理,DRAM CONTROL REGISTERS,Samsung S3C4510B,系统管理,DRAM CONTROL REGISTERS,Col:9,Row:13,Bank:2,SIZE:=16M,CPU,内部地址信号,A0-A8 A9-A21 A22,Col Row Bnk,引脚信号,A0-A8 A0-A12 A13,对照上表,CAN,应为,01,Samsung S3C4510B,系统管理,DRAM REFRESH AND EXTERNAL I/O,CONTROL REGISTER(R