计算机组成原理实验_乘法器.docx

学院 计算机组成原理 实验报告年级 学号 姓名 成绩 专业 实验地点 指导教师 实验项目 乘法器 实验日期 一 实验目的：理解并掌握乘法器的原理二 实验步骤（1） 打开QuartusII。（2） 将子板上的JTAG端口与PC机的并行口用下载电缆连接。打开实验台电源。（3） 执行 ToolsProgrammer命令，将shifter.sof下载到FPGA中。注意在执行Programmer命令中应在Programmer/configure下的方框中打勾，然后下载。（4） 在实验台上通过模式开关选择FPGA-CPU独立调试模式010.（5） 将短路子DZ3短接且短路子DZ4 断路。使FPGA-CPU所需要的时钟使用正单脉冲时钟。三 实验代码-实验6.6 Booth乘法器LIBRARY IEEE;USE IEEE.Std_logic_1164.ALL;ENTITY booth_multiplier IS GENERIC(k : POSITIVE := 3); -input number word length less one PORT( multiplicand : IN BIT_VECTOR(k DOWNTO 0); multiplier : IN BIT_VECTOR(k DOWNTO 0); clock : IN BIT; product : INOUT BIT_VECTOR(2*k + 2) DOWNTO 0); final : OUT BIT );END booth_multiplier;ARCHITECTURE structural OF booth_multiplier ISSIGNAL mdreg : BIT_VECTOR(k DOWNTO 0);SIGNAL adderout : BIT_VECTOR(k DOWNTO 0);SIGNAL carries : BIT_VECTOR(k DOWNTO 0);SIGNAL augend : BIT_VECTOR(k DOWNTO 0);SIGNAL tcbuffout : BIT_VECTOR(k DOWNTO 0);SIGNAL adder_ovfl : BIT;SIGNAL comp : BIT;SIGNAL clr_md : BIT; SIGNAL load_md : BIT;SIGNAL clr_pp : BIT;SIGNAL load_pp : BIT;SIGNAL shift_pp : BIT;SIGNAL boostate : NATURAL RANGE 0 TO 2*(k + 1) :=0;BEGINPROCESS -main clocked process containing all sequential elementsBEGIN WAIT UNTIL (clockEVENT AND clock = 1); -register to hold multiplicand during multiplication IF clr_md = 1 THEN mdreg 0); ELSIF load_md = 1 THEN mdreg = multiplicand; ELSE mdreg = mdreg; END IF; -register/shifter accumulates partial product values IF clr_pp = 1 THEN product 0); product(k+1) downto 1) = multiplier; ELSIF load_pp = 1 THEN product(2*k + 2) DOWNTO (k + 2) = adderout; -add to top half product(k+1) DOWNTO 0) = product(k+1) DOWNTO 0); -refresh bootm half ELSIF shift_pp = 1 THEN product = product SRA 1; -shift right with sign extend ELSE product = product; END IF;END PROCESS;-adder adds/subtracts partial product to multiplicandaugend = product(2*k+2) DOWNTO (k+2);addgen : FOR i IN adderoutRANGE GENERATE lsadder : IF i = 0 GENERATE adderout(i) = tcbuffout(i) XOR augend(i) XOR product(1); carries(i) = (tcbuffout(i) AND augend(i) OR (tcbuffout(i) AND product(1) OR (product(1) AND augend(i); END GENERATE; otheradder : IF i /= 0 GENERATE adderout(i) = tcbuffout(i) XOR augend(i) XOR carries(i-1); carries(i) = (tcbuffout(i) AND augend(i) OR (tcbuffout(i) AND carries(i-1) OR (carries(i-1) AND augend(i); END GENERATE; END GENERATE; -twos comp overflow bit adder_ovfl = carries(k-1) XOR carries(k);-true/complement buffer to generate twos comp of mdregtcbuffout = NOT mdreg WHEN (product(1)=1) ELSE mdreg;-booth multiplier state counterPROCESS BEGIN WAIT UNTIL (clockEVENT AND clock = 1); IF boostate 2*(k + 1) THEN boostate = boostate + 1;final =0; ELSE final =1; boostate = 0; END IF;END PROCESS;-assign control signal values based on state PROCESS(boostate)BEGIN -assign defaults, all registers refresh clr_md = 0; load_md = 0; clr_pp = 0; load_pp = 0; shift_pp = 0; -boostate =0; IF boostate = 0 THEN load_md = 1; clr_pp = 1; ELSIF boostate MOD 2 = 0 THEN -boostate = 2,4,6,8 . shift_pp = 1; ELSE -boostate = 1,3,5,7. IF product(1) = product(0) THEN NULL; -refresh pp ELSE load_pp = 1; -update product END IF; END IF;END PROCESS;END structural;四 实验现象本实验实现4位数Booth乘法（有符号的乘除法）。输入输出规则如下：（1） 输入4位被乘数md3md0对应开关SD11SD8.（2） 输入4位乘数mr3mr0对应开关SD3SD0.（3） 按单脉冲按钮，输入脉冲。（4） 乘积p8p0对应灯A8A0 。（5） 当计算结束时，final信号为1，对应灯R7.重复步骤被乘数（md）积（p）被乘数是乘数是0初始值100100000110011：00nop10010000011002：积右移一位100100000011021：10积=积-被乘数10010111001102：积右移一位100100111001131：11nop10010011100112：积右移一位100100011100141：01积=积+被乘数10011010110012：积右移一位1001110101100重复步骤被乘数（md）积（p）被乘数是乘数是0初始值110