外文翻译---微机系统

中文 2330 字 THE MICROPROCESSOR SYSTEM A microprocessor system can be described at a number of different levels of complexity. The least complex from is that of a simple block diagram describing the interconnection and flow of information functional blocks and will be used to examine the operation of a microprocessor system. All microprocessor systems contain a central processing unit(CPU),program and data memory and input(I/O) devices.Fig.4-4 show a block diagram of a typical embedded microprocessor system in which each block corresponds roughly to the individual integrated circuit(chip) used in the system. The memory section contains both non-volatile read only memory(ROM) as program memory and volatile random access memory(RAM) as read/write data memory .For each type of memory there are a number of different types of devices ,such as erasable ROMs and static or dynamic RAMs, each of which is chosen for an application based on its cost and function. Four different I/O functions are shown in Fig.4-4.An analogue input channel to the microprocessor system is provided by the analogue to digital(A/D) converter and may be used to connect a device such as an analogue to digital(A/D) converter and may be used to connect a device such as an analogue sensor. An analogue output channel is provided by the digital to analogue(D/A) converter and could be used to control an output transducer such as an electric motor, The parallel I/O device provides a number of individual lines. In output mode these can be programmed to provide logic levels 1 or 0 to activate binary(on/off)devices such as lamps. In input mode it allows the microprocessor to read the state of switches and other binary devices. The serial I/O device is used to provide communications with other microprocessor systems or with an operator console used to configure the system for various operational modes. The level and power specifications of the interfacing signals of the microprocessor system are frequently incompatible with the signal specifications of the devices which are to be interfaced to it .For example, the output voltage of a D/A converter may typically be in the range 0-5 volts and be capable of supplying only a few milliamperes of current, Fig.4-4 Block diagram of a typical embedded microprocessor system while the electric motor may require a control voltage range of plus and minus 12 volts at a maximum current of 1 ampere. Consequently, additional analogue interface circuitry is often necessary to perform functions such as signal level shifting, amplification and filtering. Fig.4-4 also shows there peripheral circuits: an input control unit(ICU),a programmable counter/timer, and a direct memory access unit(DMA).All this devices are interfaced to the CPU by means of a system bus which is itself made up from an address bus and a control bus. Physically, a bus is simple a collection of parallel interconnections between to or more devices. The number of lines contained in each bus is dependent on the type of microprocessor used in the system and the function of the bus. In Fig.4-4 we assume that the address bus has sixteen lines, the data bus has eight lines ,and the control bus contains an arbitrary number of lines depending on the control functions provided by the CPU. The concepts of address and data are fundamental to the operation of a stored program computer and form a feature of all microprocessors and computers. The memory will consist of a number of memory locations capable of storing data written to them by the CPU over the data bus .Each memory location is uniquely identified to the CPU by a number called its address. The CPU controls the address and control bus lines in order to write or read information to or form the memory or I/O devices. For example, if the CPU wished to write the binary number 01010101 into a memory location which had the address 0000000000001111,the CPU would first place the address on to the address bus, then place the number 01010101 as data onto the data bus. Controls lines in the control bus would then be activated to cause the data to be loaded into the appropriate memory location. A similar procedure would be used if the CPU was then to read a memory address, except this the flow of data would be from the memory to the CPU. After the CPU had placed the address of the required memory location on to the address bus .it would indicate to the memory that it wished to read the value by activating the relevant line in the control bus .The memory would respond by placing the contents of the memory location ad data on to the data bus ,and this would then be read by the CPU. Within the system bus, the address bus is an output bus from the CPU and an input bus to the other devices. The control bus consists of a number of lines, each of which may be either a control output from the CPU or a control input to the CPU. The data bus however acts as both an input bus and an output bus depending on whether the CPU is reading or writing data.Fig.4-4 shows that all devices in the system are connected together by the data bus and this means that, potentially at least, the outputs of all the memory and I/O devices are connected. If this were in fact to happen it would cause the destruction of several or all of the connected devices, because some devices would be trying to drive the bus to a logic 1 state while others were trying to drive it to a logic 0 state2.To avoid this problem, the data bus connections of each device are capable of being placed into a third, high impedance state where the device no longer has any loading effect on the bus. This allows other devices connected to the data bus to output their data on to this bus when they are correctly enabled, which in turn means that only one device should be enabled at any one time to the data bus3.The ability of a device to be either at a logic I or at a logic 0 or in a high impedance condition in relation to the data bus is called a tristate condition, and is an essential feature of devices which share a common data bus . In the example of Fig.4-4 the data bus has eight lines, and hence the range of values which a single item of data can take is restricted to that which can be represented by 8 binary digits or bits. Eight bits are referred to as a byte, and can represent a decimal number from 0 to 255;Likewise the address bus ,consisting of sixteen lines, can represent an address number in the range 0 to 65535.This number is usually abbreviated to the binary equivalent of the decimal number and expressed as 64K,where K is equal to 1024 in the binary number system. To the CPU, the system appears as a series of 64K consecutive memory locations, each capable of storing an 8 bit binary value. The CPU will contain a number of registers which are used to manipulate the data and its addresses. In the example chosen, these data registers will be 8 bit registers and all data manipulations will be performed on 8 bit quantities. The CPU is therefore referred to as an 8 bit CPU, However, registers which support address manipulations need to be 16 bit registers because of the 16 bit address bus. The size of the address bus is independent of the size of the data bus ,so that 16 bit or 32 bit CPUs may typically have a 16 bit,24 bit or 32 bit address bus. It is normal when working with microprocessors to represent binary numbers as hexadecimal (base 16) values, because a single hexadecimal hex)digit corresponds to a group of four consecutive binary The hexadecimal number is easier to read and write than its binary equivalent, and it requires only simple mental calculation in order to translate from hexadecimal to binary and back again. Hexadecimal numbers and digits are identified in the text by prefixing them with Ox, which is the convention adopted in the C programming language. For example, the 16 bit binary number 1111110100111001 would be written in hexadecimal form as 0xFD39. It is not necessary for the hardware designer to make use of the entire address range of the CPU, and the physical memory required can be implemented anywhere within the address space of the CPU. In addition, the I/O devices will contain registers through which the IO devices may be configured, and which provide addresses through which the CPU can read and write data into and out of the system. These registers appear to the CPU. as normal memory location. And so occupy parts of the address space. The arrangement of the memory and I/O addresses within the address space is described by the memory map of the system, an example of which is given in Fig.4-5a. The memory map will be designed to meet the requirements of the application, and will be used by the hardware designer to partition the address space so that the address range of the memory devices in the system corresponds to the address range specified by the memory map. This is achieved by means of the address decoder. Shown in Fig.19-1,this uses lines from the address bus as its input and produces individual chip select signals for each chip which contributes to the memory map of the system.Fig.4-5a shows that the particular system under consideration should have RAM from memory location 0x1000to memory location 0x1FFF.This address range represents 4K bytes (4096) of memory, requiring the lower twelve address lines of the address bus ,All-A0,to be connected to a 4K RAM device. The remaining four upper address lines,A15-A12,are taken to the address decoder which outputs a chip select signal to the RAM whenever the lines A15-A12 have the value 0001.The address decoder therefore implements the Boolean equation RAM enable =A.15 A.14 A13.A12=A15+A14+A13+A12 (4-4) as in Fig.4-5b. From.Direction Editor Zhangyue. China machine press.1.2003 参考译文 ： 微机系统 微机系统可在许多复杂的层面上进行描述。最简单的形式是用简单的方块图来描述内部的连接以及各功能块间的信息流，并用来分析微机系统的工作情况。 所有微机系统包含一个中央处理单元（ CPU）、程序和数据存储器以及输入、输出（ I/O）设备。图 4-4 表示了一个典型的嵌入式微机系统的方框图，该图中每个方块大致上对应于该系统中所用的单个集成电路（芯片）。 存储器部分包含了用作程序存储器的掉电不易失信息的只读存储器（ ROM）和用作读 /写的掉电易失的随机访问数据存储器（ RAM），每种存储器都有许多不同类型的元件，如可擦写的 ROM 以及静态或动态 RAM，应用时，根据价格、功能来选择。 图 4-4 表示四种不同的 I/O 功能，微机系统的模拟信道由模数（ A/D）转换提供，可以连 接如模拟输入传感器这样的器件。模拟输入信道由数模（ D/A）转换器提供，可以用于控制像电动机这样的动力输出转换器。并行 I/O 元件提供许多独立的输入 /输出端口线，在输出方式下，这些端口可以通过编程提供逻辑电平 1或 0来驱动二进制（开 /关）设备如灯泡。在 输入方式下，微处理器可允许读入开关及其他的二进制设备的状态。串行 I/O设备用于与其他的微机系统或不同操作模式的操作控制台之间进行通信。 微机系统接口信号的电平和功率大小，常常与连接的元器件不匹配，例如，一个 D/A转换器典型的输出电压是 0 5V ，并仅能提供毫安培级 电流，而电动机可能要求的控制电压范围为 -12V +12V，最大电流 1A。为此需相应的增加模拟接口电路实现信号电平转换、放大和滤波。图 4-4中还表示了三个外围电路：中断控制单元（ ICU）、可编程计数 /定时器以及直接存储器访问单元（ DMA）。 所有这些元件都通过系统总线和 CPU 接口。系统总线由地址总线、数据总线和控制总线构成。实际上，总线只是两个元件间并行连接线的集合。每个总线包含的引线由系统使用的微处理器的型号以及总线的功能来确定，如图 4-4所示，我们假设地址总线为 16根，数据总线为 8 根，控制总线数目不确定 ，这要由 CPU提供的功能而定。 地址和数据是运行计算机所储存的程序、形成所有微处理器和计算机特征的基础。存储器由许多能由 CPU通过数据总线写入数据的存储单元构成。每个存储单元具体位置由 CPU 用地址来唯一标识。为了从存储器或 I/O口设备中写或读信息， CPU控制着地址和控制总线，如 CPU希望将二进制信息 01010101 写入地址为0000000000001111 的存储单元， CPU 首先将该地址送到地址总线上，然后将01010101作为数据送到数据总线上，控制总线中的控制线激活，启动数字写入适当的存储单元。相类似的情 况用于 CPU只读存储单元的地址的过程，这时数据流不是从存储器到 CPU，那么在 CPU 将要求的存储单元的地址送到地址总线上后，CPU通过启动控制总线相关的控制线，指示存储器要读数据，存储器则做出反应，将该存储单元的内容当作数据，送上数据总线，然后 CPU读取到该数据。 在系统总线中，地址总线对 CPU来说是输出总线，但对其他设备是输入总线，控制总线包含许多线，它们或者是 CPU输出控制线，或者是输入控制线。数据总线既当作输入总线，又作输出总线，这要看 CPU 是读还是写数据，图 4-4，表示了系统中所有元件都通过数据总线连 在一起，这意味着，最低限度上存储器和 I/O设备的 输出是连在一起的。如果实际情况是这样，则将引起所有连接的元件中几个或全部元件被破坏，因为一些元器件将试图驱动总线到逻辑 1 状态，而其他一些则试图驱动其为 0状态。为了避免这个问题，连接到每个元件的数据总线有