Cadence后端实验系列19版图验证Assura.ppt

Cadence 后端实验系列19_版图验证_ Assura,Introduction to Assura Physical Verication Assura Physical Verification Tool Suite Assura Task and Data Flow Assura Input Files Running Assura DRC Graphical User Interface Run Guide LVS Graphical User Interface Run Guide RCX Graphical User Interface Run Guide Demonstration,OUTLINE,Introduction to Assura Physical Verication Assura Physical Verification Tool Suite Assura Task and Data Flow Assura Input Files Running Assura DRC Graphical User Interface Run Guide LVS Graphical User Interface Run Guide RCX Graphical User Interface Run Guide Demonstration,OUTLINE,Assura Physical Verification Tool Suite,The Assura verication suite is optimized for large, hierarchical, repetitive designs such as memory, microprocessor, and mixed-signal circuits. The software upholds the Cadence verication tradition of accuracy established by its Dracula and Diva products. The Assura tools ensure accuracy and leverage the layout hierarchy of leading-edge designs to provide faster physical verication runtimes.,Assura Physical Verification Tool Suite,Assura DRC Assura DRC (Design Rule Checking) checks the layout against geometric spacing, width, and other rules. Typical checks include material spacing, enclosure, coverage, and overlap. Assura DRC displays design rule violations graphically as an additional graphics layer on the layout, and lists them in text les. Assura LVS Assura LVS (Layout Versus Schematic) comparison extracts devices and connectivity from the layout according to device extraction rules, then creates a layout netlist according to netlist rules, then nally compares the layout netlist to the schematic netlist according to comparison rules. Assura LVS displays mismatches between the layout and the schematic both textually and graphically. Assura RCX Assura RCX (Resistance, Capacitance and Inductance Extraction) extracts parasitic resistance, capacitance, and inductance from the layout for analysis and input to post-layout simulators.,Assura Task and Data Flow,Assura Input Files,Run-Specic File (RSF),The Assura RSF is a required control le in text format that directs the Assura DRC, LVS, or RCX run. It species input data les, rule les, run-specic options, and commands to invoke the tool. The Assura RSF follows Cadence SKILL language syntax. Options in an RSF are specied as parameters, which begin with a “?” followed by a keyword.,When you use the Assura Graphical User Interface (GUI), the GUI creates the RSF for you using the settings you specied in the forms, and invokes an Assura tool using this RSF. Alternatively you can create your own RSF. You can specify the RSF le name in the GUI run form, or you can specify the RSF le name on the command line if you run an Assura tool in batch mode.,Run-Specic File (RSF),The Assura RSF consists of several sections: A mandatory avParameters section One or more avCompareRules sections for an LVS run An rcxParameters section for an RCX run Optional statements outside the above sections One or more mandatory Assura tool invocation commands,The avParameters Section,The Assura RSF contains a mandatory avParameters section that species the input layout and rules le associated with the Assura run, plus various global RSF options. Below is an example of an avParameters section.,avParameters( ?workingDirectory “/usr1/drc/“ ?runName “peakDetect“ ?inputLayout ( “df2“ “design“ ) ?cellName “peakDetect“ ?technology “gold“ ?techLib “/usr1/amancuso/rcx/assura_tech.lib“ ),The avCompareRules Section,The RSF contains one or more avCompareRules sections if the RSF is for an Assura LVS run. The avCompareRules section Species the input schematic, an optional binding le for mapping layout device and net names to schematic names, and other rules and options.,avCompareRules( schematic( netlist( dfII “netlist.dfII” ) bindingFile(“bindings”) mergeSplitGate( mergeAll ) showErrorNetwork() compareParameter(MOS percent(“w” 5 “l” 5) compareParameter(“res_poly“ percent(“r“ 5) compareParameter(“res_nwell“ percent(“r“10) ),The rcxParameters Section,The RSF contains an rcxParameters section if the RSF is for an RCX run.,rcxParameters( ?runName“peakDetect“ ?extract“cap“ ?minR0.001 ?maxFractureLength“infinite“ ?fractureLengthUnits“microns“ ?capExtractMode“decoupled“ ?capGround“vss!“ ?capCouplingFactor1.0 ?type“full“ ?netNameSpace“layout“ ?outputFormat“spice“ ?output“peakDetect.sp“ ?groundNets (“vss!“ “gnd!“) ?powerNets (“vdd!“) ?tempdir “/tmp“ ?parasiticResModels “comment“,?subNodeChar “#“ ?outputNetNameSpace “schematic“ ?parasiticCapModels “yes“ ?capModels “no“ ?hierarchyDelimiter “/“ ?resModels “no“ ),RSF Statements Outside Sections,You can place optional statements in the RSF outside an avParameters, avCompareRules or rcxParameters section. These statements include several Assura rules that can optionally be placed in an RSF, user-supplied SKILL functions, and Assura tool invocation commands.,Assura Tool Invocation Commands,The Assura RSF must end with one or more Assura tool invocation commands that launch the appropriate verication tasks. When an Assura tool is run from the GUI, the appropriate invocation command is placed at the end of the RSF. If you create your own RSF, you can nest parameter sections within the invocation command to specify parameters that apply to that command only.,Rule Files,Assura tools require a set of rules to guide their operation. Rule les are text les. Rules are grouped together in the rule le within separate sections enclosed in parentheses. Assura rules follow the syntax of the Cadence SKILL programming language. Assura rule les can be located anywhere in your le system, and they do not have default names. The following table lists the standard rule les used with each tool:,Assura DRC Rules,Within an Assura drc.rul le, DRC rules are contained in a drcExtractRules section.,drcExtractRules( layerDefs( “df2“ nwell = layer( “nwell“ type(“drawing“) poly1 = layer( “poly1“ type(“drawing“) pwell = layer( “pwell“ type(“drawing“) metal1 = layer( “metal1“ type(“drawing“) metal2 = layer( “metal2“ type(“drawing“) contact = layer( “cont“ type(“drawing“) via = layer( “via“ type(“drawing“) ndiff = layer( “ndiff“ type(“drawing“) pdiff = layer( “pdiff“ type(“drawing“) text = text(“text“ type(“drawing“) ) ;end layerDefs,layerDefs( “gds2“ nwell = layer( 12) poly1 = layer( 35) pwell = layer( 6) metal1 = layer( 45) metal2 = layer( 50) contact = layer( 55) via = layer( 8) ndiff = layer( 1) pdiff = layer( 2) text = text(62) ) ;end layerDefs,The rst step is identifying the physical design layers contained in the input layout data .,Layer Denition Rules,Layer Derivation Rules,ngate = geomAnd( ndiff poly1 ) ngate layer = ndiff AND poly1 pgate = geomAnd( pdiff poly1 ) ndiff = geomAndNot( ndiff poly1 ) pdiff = geomAndNot( pdiff poly1 ); pdiff = orig pdiff not including pdiff under poly1 ptap = geomAndNot( pdiff nwell ) ; ptap = derived pdiff less pdiff in nwell ntap = geomAnd( ndiff nwell ),The next step in specifying DRC rules is to derive additional layers from the original input layers to allow the tool to test the design against specic foundry requirements. The Assura program provides several logical operation rules that can be applied to existing layers to derive new layers. For example, MOSFET gate regions, well taps and substrate ties, as well as the substrate bulk, can be derived from the original layer information with Assura logical operation rules (layer derivation rules also are called layer processing rules).,DRC Design Check Rules,Following is a sample list of design checks for poly1 and metal1 layers.,check poly1 errpolysep = drc(poly1 sep1 “poly1 spacing lt 1“) errorLayer(errpolysep) errpolywid = drc(poly1 width1 “poly1 width lt 1“) errorLayer(errpolywid) errpolynotch = drc(poly1 notch1 “poly1 notch lt 1“) errorLayer(errpolynotch) errpolycont = drc(poly1 contact enc .5 “poly1/contact enclosure lt .75“) errorLayer(errpolycont) errpolydiffsep = drc(poly1 diff sep 1 “poly1/diff spacing lt 1“),errorLayer(errpolydiffsep) end poly1 checks check metal1 errmet1sep = drc(metal1 sep1 “metal1 spacing lt 1“) errorLayer(errmet1sep) drc(metal1 width1 “metal1 width lt 1“) drc(metal1 notch1 “metal1 notch lt 1“) drc(metal1 contact enc .5 “metal1/contact enclosure error“) drc(metal1 via enc .5 “Metal1/via enclosure error“) end metal1 checks,DRC Design Check Rules,Assura LVS Rules,LVS Extract Rules,The LVS extract rules, typically contained in an extract.rul le, contain the information necessary for Assura LVS to extract drawn devices and connectivity information from the layout geometry data input to Assura LVS. This extracted device and connectivity information is output by the Assura program in a layout netlist, which Assura LVS compares to the input schematic netlist.,LVS Connectivity Rules,Connectivity rules are added to the drcExtractRules section to establish connectivity between the dened and derived layout layers. Among other rules, the geomConnect and geomStamp commands are used for this purpose,For example: geomConnect( via( cont poly1 ndiff pdiff metal1 ntap ptap) via( via metal1 metal2 ) label( text poly1 metal1 metal2 ) label( polytext poly1) label( met1text metal1) label( met2text metal2) ) geomStamp(psubcon ptap error) geomStamp(nwellcon ntap error),LVS Device Extraction Rules,Device extraction rules are added to the drcExtractRules section of the LVS extract.rul le. These rules tell Assura LVS how to extract specic devices, such as MOSFETs, LDDs, and BJTs, and their associated device terminals, from the dened layout layers.,For example: extractMOS( “nfet“ ngate poly1(“G“) ndiff(“S“ “D“) psubcon(“B“) 1 flagMalformed ) extractMOS( “pfet“ pgate poly1(“G“) pdiff(“S“ “D“) nwellcon(“B“) 1 flagMalformed ),LVS Parameter Extraction Rules,Additional extract rules can be added to the drcExtractRules section to direct Assura LVS to measure and extract layout device parameters, such as MOSFET width and length parameters.,LVS Compare Rules,Assura LVS comparison rules include all the rules associated with comparing a layout netlist to a schematic netlist. The rules include run control options, input schematic specication, and rules governing device parameter comparison.,avParameters ( ?inputLayout () ?cellName () ; end of avParameters avCompareRules ( general_rules schematic ( ;netlist specification-required netlist (),other network_specific_rules ) layout ( network_specific_rules ) bindingFile (“/usr1/gold_tech/bind.rul“) ); end of avCompareRules,Assura RCX Rules,There are three primary data les used to dene the RCX rules: 1. The process le, which provides technology-based capacitance modeling information 2. The lvsfile, which is a converted LVS extract.rul le that provides LVS device and connectivity information to Assura RCX 3. The p2lvsfile, which matches the process le to the lvsle, and also provides technology-based resistance modeling information,Running Assura,You can run Assura as an interactive graphical tool or as a batch tool from the Unix command line. Assura requires a text input le called the run-specic le (RSF) for each run. When you use the Assura graphical user interface (GUI), the GUI creates the RSF and starts the Assura run. When you start Assura as a batch tool you must specify an RSF.,Running Assura Tools From the DFII GUI,Launch the Cadence DFII executable (icfb),Select File-Open. from the DFII Command Interpreter Window (CIW) as shown below.,Select the library, and top cell name of the design, then select layout view, then click OK to open the layout view in the Virtuoso Layout Editor (see below).,After you have selected the design, the layout view opens in the Virtuoso layout editor.,Running Assura Tools From the DFII GUI,Running Assura Tools From the DFII GUI,Introduction to Assura Physical Verication Assura Physical Verification Tool Suite Assura Task and Data Flow Assura Input Files Running Assura DRC Graphical User Interface Run Guide LVS Graphical User Interface Run Guide RCX Graphical User Interface Run Guide Demonstration,OUTLINE,DRC Run Guide,DRC Run Guide,DRC Run Guide,Cell name is the name of the top cell of the layout you want to verify.,Input File name is the le containing the Stream design to check. This eld is available only if you select Stream as the layout format.,DRC Run Guide,Run Name is the Name you want to use to refer to this Assura DRC run. If you do not specify a run name, the Assura program uses the cell name of the design. All output les contain this name as a prex. Run Directory is the full or relative path to the run directory. If the directory you specify does not exist, Assura DRC creates the directory. Run Location is where you can select either a local or remote machine for a DRC run.,DRC Run Guide,Switch Names Identies the section of statements in the rules le that you want to use for a specic Assura DRC or circuit extraction to control the command stream. To identify the switches that you want to use for an Assura DRC run, type the switch names in the Switch Names eld. You must type at least one space between multiple switch names. For example:drc1 substratecheck,Set Switches Click on Set Switches to open the Set Switches form to view the available switches in the specied rules le. Select a switch by clicking on the name of the switch; select more than one switch by holding down the Control key and clicking on each switch name and then click OK.,DRC Run Guide,RSF Include The RSF Include eld allows you to specify an additional RSF le to be included into the top-level RSF being created by the DRC User Interface. When the specied Technoloy denes an include le using the DrcInclude keyword, this le is automatically loaded into the RSF Include eld, and the eld is grayed out so that it cannot be modied.