《集成电路设计举例》PPT课件.ppt

18.1 MOS集成电路的正向设计 18.1.1 74HC139电路简介 18.1.2电路设计 18.1.3工程估算 18.1.4电路模拟 18.1.5版图设计 18.1.6版图检查,集成电路的正向设计,集成电路的正向设计,1 MOS集成电路的正向设计 1.1 74HC139电路简介 2-4译码器：,74HC139,Cs A1 A0 Y1 Y2 Y3 Y4 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 x x 1 1 1 1,Y0=Cs+A1+A0=,Y1=Cs+A1+,=,Y2=Cs+,+A0=,Y3=Cs+,+,=,1.2 电路的设计,1 输出级电路设计 与TTL电路兼容 驱动10个TTL 输出高电平时IoH=20 VoHmin=4.4V 输出低点平时IoH=4 m VoHmax=0.4V 输出级充放电时间tr=tf,15 pF,计算电路如图所示 以15个PF的电容负载代替10个TTL电路来计算tr、tf 输入V为的前一级的输出被认为是理想的输出，即：ViL=Vss,ViH=Vdd 计算电流时，负载为电流负载，有拉电流的灌电流。,（1）CMOS N管（W/L）N的计算 当输入为高电平时（Vi=Vdd）,N管导通后级TTL电路有较大的灌电流输入，此时（表示成对称形式）,使方括号中的值和栅电容Cox及电子迁移率un为最小值:,IDSn= 20m uN0= 530 Tox=7E-8 Vto=0.7 V=4.4 Vi=5,(2) CMOS P管（W/P）p的计算 IoH=20时有 VoHmin=4.4V tr=tf 以Ioh=20时VoHmin=4.4V的条件计算,最坏的情况下 Vdd=4.5V,Vohmin=4.4v,Vtp=0.8V,经计算可得,tr=tp的条件计算：CMOS中,所以,p=n,2、输入级设计 输入电平Vih可能为2.4V （1）拉管P2 为了节省面积，同时又能使Vih较快上升，取,(2)CMOS反向器的P1管 此P1管应取内部基本反向器的尺寸,（3）CMOS反相器的N管 TTL的输出电平在0.4-2.4之间 V1*=ViLmax+Vihmin=1.4V,式中 R=kn/kp, Vdd=5V, Vtn=0.7V, Vtp=-0.7V, Vi*=1.4V, R=17.16,3、内部基本反相器中各MOS管尺寸的计算,内部反相器的负载电容： 本级漏极的PN结电容Cpn 下级的栅电容Cc1 连线杂散电容Cs Cpn+Cc1=10Cs Cs :铝线宽5um,长100um，在场区上面，此铝线的电容为,Cpn 和Cl：,N管 其衬底是P型，所以 NB=21016 cm-3 设结深Xi=0.5um R=20/,对于P管,Cpn=,而CC1可以由：Cc1=10Cs-Cpn求出。 下面具体计算N管和P管的尺寸。 N管单位尺寸电阻为 ，总电阻为 ， P管单位尺寸电阻为 ，总电阻为 。 总电容C=Cpn+Cc1+Cs=Cpn+Cc1 Cc1=(Wn+Wp)LCox=10Cs-aWnCpn,对于P管：,Cpn=,a,Wn,a为有源区宽度，因为最小孔为3*3， 孔与等晶栅的间距为2，孔与有源区边界的间距为1（1=1.5um）， 所以a=6=9um,上升时间：tr= 下降时间：tf=,Wp=kWn,Wn=,=21um=14,Wp=kWn=46.5um=31,N管放大三倍,4、内部逻辑门设计,5、缓冲级的设计,（1）输入缓冲级,M2,M1,M3,M1为输入级，M2为内部门，M3为缓冲器,三输入与非门尺寸：,M3负载的栅面积：,M2负载的栅面积：,扇出系数N=,N=,加入一级缓冲后，管子逐级放大的尺寸为,=2.597,M3管子尺寸为,=36/2,内部反相器的尺寸为,n2=21/3=14/2,p2=46.5/3=31/2,=79/2,(2)输出缓冲级,M2,M1,M0,缓冲级M1的计算：,由,及N的值可得,6、输入保护电路的设计,二极管的有效面积取500m2,.model nmos nmos + Level=2 Ld=3.0E-7 Tox=225.00E-10 + Nsub=2E+16 Vto=0.7 Kp=2.61E-05 + Gamma=1.652 Phi=0.73 Uo=530.0 + Uexp=0.104 Ucrit=6E4 Delta=8.0 + Vmax=1E5 Xj=5.0E-7 Lambda=0.03 + Nfs=4.55168E+12 Neff=3 Nss=3.00E+10 + Tpg=1.000 Rsh=60 Cgso=1.97E-10 + Cgdo=1.97E-10 Cj=4.2E-04 Mj=0.5 + Cjsw=1.E-10 Mjsw=0.195 .model pmos pmos + Level=2 Ld=2.0E-7 Tox=7.0E-8 + Nsub=5.0E+15 Vto=-0.7 Kp=1.13E-05 + Gamma=0.826 Phi=0.66 Uo=230 + Uexp=0.15 Ucrit=6.0E+4 Delta=8.0 + Vmax=5E+4 Xj=8E-7 Lambda=0.03 + Nfs=1.668437E+11 Neff=3.0 Nss=3.00E+10 + Tpg=-1.00 Rsh=150 Cgso=1.97E-10 + Cgdo=1.97E-10 Cj=2.2E-04 Mj=.341 + Cjsw=2.23E-10 Mjsw=0.307,VTO (VT):Zero-bias threshold voltage. If you do not specify VTO, simulation calculates it. KP: Intrinsic transconductance parameter. If you specify U0 and TOX, but you do not specify KP, simulation computes the parameter from: KP = UO COX. Level 1 default=2.0718e-5 (NMOS), 8.632e-6 (PMOS). level 2, 3 default=2.0e-5 GAMMA: Body effect factor. If you do not set GAMMA, simulation calculates it from NSUB. PHI:Surface inversion potential. If you do not specify PHI, HSPICE calculates it from NSUB. (V) PB:Source/drain bulk junction potential. CGSO (CGS, C1):Gate-source overlap capacitance per meter channel width. If you set LD or METO and TOX, but you do not set CGSO, then simulation calculates CGSO. CGSOscaled = CGSO/SCALM (F/m) CGDO (CGD, C2): Gate-drain overlap capacitance per meter channel width. If you set LD or METO and TOX, but you do not set CGDO, then simulation calculates CGDO. CGDOscaled = CGDO/SCALM (F/m) CGBO (CGB):Gate-bulk overlap capacitance per meter channel length. If you set WD and TOX, but you do not set CGBO, then simulation calculates CGBO. CGBOscaled = CGBO/SCALM,CJ (CDB, CSB, CJA):Zero-bias bulk junction capacitance: CJscaled = CJ/SCALM2 for ACM=1 the unit is F/m. CJscaled = CJ/SCALM. Default for the ASPEC=0 option is: MJ: Source/drain bulk junction grading coefficient. RSH:Source/drain sheet resistance. UO: Low-field bulk mobility.Simulation calculates this parameter from the KP value that you specify. VMAX (VMX, VSAT):Maximum drift velocity of the carriers. Zero indicates an infinite value. Default VMAX value for Level 40 is 1e6 (m/s) TOX: Oxide thickness, calculated from COX (if you specify COX). The program uses the default if you do not specify COX. For TOX1, simulation assumes that the unit is Angstroms. A level-dependent default can override it. See specific MOSFET levels in this manual. NSUB (DNB, NB): Substrate doping. TPG (TPS): Type of gate material, for analytical models. LEVEL 4 TPG default=0. The TPG value can be: TPG = 0 al-gate. TPG = 1 same as source-drain diffusion. TPG = -1 gate type opposite to source-drain diffusion.,XJ: Metallurgical junction depth: XJscaled = XJ SCALM LD (DLAT,LATD):Lateral diffusion into the channel from the source and drain diffusion. If you do not specify LD and XJ, LD default=0.0. If you specify LD, but you do not specify XJ, then simulation calculates LD from XJ. Default=0.75 XJ. For LEVEL 4 only, lateral diffusion is derived from LD XJ. LDscaled = LD SCALM XQC: Coefficient of channel charge share attributed to drain; its range is 0.0 to 0.5. This parameter applies only to CAPOP=4 and some of its level-dependent aliases. DELTA: Narrow width factor for adjusting the threshold. LAMBDA:Channel length modulation.,工程估算,1.模型简化 四个三输入与非门中只有一个可被选通并工作,而另三个不工作,所以在C3端经三级反相器后,将不工作的三输入与非门等效为负载电容CL1,与非门的两个输入接高电平,只将C3端信号加在反相器上,因此计算X点之后的部分.X点以前的部分CS这一条之路,最后将结果乘以3倍就可以了.,从输入到输出的所有各支路中,只有C3端加入了缓冲级因而增加了延时与功耗,因此估算考虑最坏的情况,输入门,三输入与非门,输出门,输入缓冲门,内部门,输出缓冲门,2.功耗计算,静态功耗.瞬态功耗,交变功耗,只考虑瞬态功耗 PT=CL总fC(VOHVOL)VDD,CL总,4路三输入与非门的栅作为前级负载,COX考虑最坏情况,故取,设工作频率,3.延迟估算,定义每级反相器，充电时间常数为,放电时间常数为：,于是,充电时间,放电时间,u为从低电平充到高电平的归一化电平,u为从高电平放电到低电平的归一化电平。 估算中取值,一级反相器的延时为：,（1）指标要求：输出级