基于AT89C52单片机的交通灯控制系统设计(外文翻译).doc

电子与信息工程学院 本科毕业论文(设计)外 文 文 献 翻 译译文题目： 8-bit microcontroller with 8k bytes flash at89c52 学生姓名： 吴远超 专 业： 电气工程及其自动化 指导教师： 倪 浩 2012年11月 外文资料8-bit microcontroller with 8k bytes flash at89c52featurescompatible with mcs-51 products8k bytes of in-system reprogrammable flash memoryendurance: 1,000 write/erase cyclesfully static operation: 0 hz to 24 mhzthree-level program memory lock256 x 8-bit internal ram32 programmable i/o linesthree 16-bit timer/counterseight interrupt sourcesprogrammable serial channellow-power idle and power-down modesdescriptionthe at89c52 is a low-power, high-performance cmos 8-bit microcomputer with 8k bytes of flash programmable and erasable read only memory (perom). the device is manufactured using atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80c51 and 80c52 instruction set and pin out. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. by combining a versatile 8-bit cpu with flash on a monolithic chip, the atmel at89c52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.pin configurationsblock diagrampin descriptionvccsupply voltage.gndground.port 0port 0 is an 8-bit open drain bi-directional i/o port. as an output port, each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as high-impedance inputs. port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. in this mode, p0 has internal pull-ups. port 0 also receives the code bytes during flash programming and outputs the code bytes during program verification. external pull-ups are required during program verification.port 1port 1 is an 8-bit bi-directional i/o port with internal pull-ups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil) because of the internal pull-ups. in addition, p1.0 and p1.1 can be configured to be the timer/counter 2 external count input (p1.0/t2) and the timer/counter 2 trigger input (p1.1/t2ex), respectively, as shown in the following table. port 1 also receives the low-order address bytes during flash programming and verification. port 2port 2 is an 8-bit bi-directional i/o port with internal pull-ups. the port 2 output buffers can sink/source four ttl inputs. when 1s are written to port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (iil) because of the internal pull-ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memories that use 16-bit addresses (movx dptr). in this application, port 2 uses strong internal pull-ups when emitting 1s. during accesses to external data memories that use 8-bit addresses (movx ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3port 3 is an 8-bit bi-directional i/o port with internal pull-ups. the port 3 output buffers can sink/source four ttl inputs. when 1s are written to port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (iil) because of the pull-ups.port 3 also serves the functions of various special features of the at89c51, as shown in the following table. port 3 also receives some control signals for flash programming and verification.rstreset input. a high on this pin for two machine cycles while the oscillator is running resets the device.ale/address latch enable is an output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input () during flash programming. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode.program store enable is the read strobe to external program memory. when the at89c52 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memory./vppexternal access enable. must be strapped to gnd in order to enable the device to fetch code from external program memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, will be internally latched on reset. ea should be strapped to vcc for internal program executions. this pin also receives the 12-volt programming enable voltage (vpp ) during flash programming when 12-volt programming is selected.xtal1input to the inverting oscillator amplifier and input to the internal clock operating circuit.xtal2output from the inverting oscillator amplifier.special function registersa map of the on-chip memory area called the special function register (sfr) space is shown in the table 1.note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. user software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. in that case, the reset or inactive values of the new bits will always be 0.timer 2 registers control and status bits are contained in registers t2con and t2mod for timer 2. the register pair (rcap2h, rcap2l) are the capture/reload registers for timer 2 in 16-bit capture mode or 16-bit auto-reload mode.interrupt registers the individual interrupt enable bits are in the ie register. two priorities can be set for each of the six interrupt sources in the ip register.data memorythe at89c52 implements 256 bytes of on-chip ram. the upper 128 bytes occupy a parallel address space to the special function registers. that means the upper 128 bytes have the same addresses as the sfr space but are physically separate from sfr space.when an instruction accesses an internal location above address 7fh, the address mode used in the instruction specifies whether the cpu accesses the upper 128 bytes of ram or the sfr space. instructions that use direct addressing access sfr space. for example, the following direct addressing instruction accesses the sfr at location 0a0h .mov 0a0h, #datainstructions that use indirect addressing access the upper 128 bytes of ram. for example, the following indirect addressing instruction, where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h).mov r0, #datanote that stack operations are examples of indirect addressing, so the upper 128 bytes of data ram are available as stack space.timer 0 and 1timer 0 and timer 1 in the at89c52 operate the same way as timer 0 and timer 1 in the at89c51.timer 2timer 2 is a 16-bit timer/counter that can operate as either a timer or an event counter. the type of operation is selected by bit c/t2 in the sfr t2con.timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. the modes are selected by bits in t2con, as shown in table 3.timer 2 consists of two 8-bit registers, th2 and tl2. in the timer function, the tl2 register is incremented every machine cycle. since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t2. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. to ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.capture modein the capture mode, two options are selected by bit exen2 in t2con. if exen2 = 0, timer 2 is a 16-bit timer or counter which upon overflow sets bit tf2 in t2con.this bit can then be used to generate an interrupt. if exen2 = 1, timer 2 performs the same operation, but a 1-to-0 transition at external input t2ex also causes the current value in th2 and tl2 to be captured into rcap2h and rcap2l, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set. the exf2 bit, like tf2 can generate an interrupt. the capture mode is illustrated in figure 1.auto-reload (up or down counter)timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. this feature is invoked by the dcen (down counter enable) bit located in the sfr t2mod. upon reset, the dcen bit is set to 0 so that timer 2 will default to count up. when dcen is set, timer 2 can count up or down, depending on the value of the t2ex pin.figure 2 shows timer 2 automatically counting up when dcen = 0. in this mode, two options are selected by bit exen2 in t2con. if exen2 = 0, timer 2 counts up to 0ffffh and then sets the tf2 bit upon overflow. the overflow also causes the timer registers to be reloaded with the 16-bit value in rcap2h and rcap2l. the values in timer in capture modercap2h and rcap2l are preset by software. if exen2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input t2ex. this transition also sets the exf2 bit. both the tf2 and exf2 bits can generate an interrupt if enabled. setting the dcen bit enables timer 2 to count up or down, as shown in figure 3. in this mode, the t2ex pin controls the direction of the count. a logic 1 at t2ex makes timer 2 count up. the timer will overflow at 0ffffh and set the tf2 bit. this overflow also causes the 16-bit value in rcap2h and rcap2l to be reloaded into the timer registers, th2 and tl2, respectively. a logic 0 at t2ex makes timer 2 count down. the timer underflows when th2 and tl2 equal the values stored in rcap2h and rcap2l. the underflow sets the tf2 bit and causes 0ffffh to be reloaded into the timer registers. the exf2 bit toggles whenever timer 2 overflows or underflows and can be used as a 17th bit of resolution. in this operating mode, exf2 does not flag an interrupt.外文资料译文：8位8字节闪存单片机at89c52主要性能l 与mcs-51单片机产品兼容l 8k字节在系统可编程flash存储器l 1000次擦写周期l 全静态操作：0hz24hzl 三级加密程序存储器l 2568位内部存储器l 32个可编程i/o口线l 三个16位定时器/计数器l 八个中断源l 可编程串行通道l 低功耗空闲和掉电模式功能特性描述at89s52是一种低功耗、高性能cmos8位微控制器，具有8k内置可编程闪存。产品使用了atmel公司高密度非易失性存储器技术制造，与工业80c51和80c52产品指令和引脚完全兼容。片上flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8位cpu和在系统可编程flash，使得at89s52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。引脚结构方框图vcc : 电源gnd : 地p0口：p0口是一个8位漏极开路的双向i/o口。作为输出口，每位能驱动8个ttl逻辑电平。对p0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，p0口也被作为低8位地址/数据复用。在这种模式下，p0具有内部上拉电阻。在flash编程时，p0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。p1口：p1 口是一个具有内部上拉电阻的8位双向i/o 口，p1 输出缓冲器能驱动4个ttl 逻辑电平。对p1端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（iil）。此外，p1.0和p1.2分别作定时器/计数器2的外部计数输入（p1.0/t2）和时器/计数器2的触发输入（p1.1/t2ex），具体如下表所示。在flash编程和校验时，p1口接收低8位地址字节。p2 口：p2 口是一个具有内部上拉电阻的8 位双向i/o 口，p2输出缓冲器能驱动4个ttl 逻辑电平。对p2端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（iil）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行movx dptr）时，p2口送出高八位地址。在这种应用中，p2口使用很强的内部上拉发送1。在使用8位地址（如movx ri）访问外部数据存储器时，p2口输出p2锁存器的内容。在flash编程和校验时，p2口也接收高8位地址字节和一些控制信号。p3 口：p3口是一个具有内部上拉电阻的8 位双向i/o 口，p2输出缓冲器能驱动4个ttl 逻辑电平。对p3端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（iil）。p3口亦作为at89s52特殊功能（第二功能）使用，如下表所示。在flash编程和校验时，p3口也接收一些控制信号。rst: 复位输入。晶振工作时，rst脚持续2个机器周期高电平将使单片机复位。看门狗计时完成后，rst脚输出96个晶振周期的高电平。特殊寄存器auxr(地址8eh)上的disrto位可以使此功能无效。disrto默认状态下，复位高电平有效。ale/：地址锁存控制信号（ale）是访问外部程序存储器时，锁存低8位地址的输出脉冲。在flash编程时，此引脚（）也用作编程输入脉冲。在一般情况下，ale 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ale脉冲将会跳过。如果需要，通过将地址为8eh的sfr的第0位置“1”，ale操作将无效。这一位置“1”，ale 仅在执行movx 或movc指令时有效。否则，ale 将被微弱拉高。这个ale 使能标志位（地址为8eh的sfr的第0位）的设置对微控制器处于外部执行模式下无效。:外部程序存储器选通信号（）是外部程序存储器选通信号。当 at89s52从外部程序存储器执行外部代码时，在每个机器周期被激活两次，而在访问外部数据存储器时，将不被激活。/vpp:访问外部程序存储器控制信号。为使能从0000h 到ffffh的外部程序存储器读取指令，必须接gnd。为了执行内部程序指令，应该接vcc。在flash编程期间，也接收12伏vpp电压。xtal1:振荡器反相放大器和内部时钟发生电路的输入端。xtal2:振荡器反相放大器的输出端。特殊功能寄存器如图1中所示的存储器区域称为特殊功能寄存器。应该注意到，并不是所有的地址都会被定义，单片机中那些没有被定义的地址是无效的。读访问这些地址一般会返回随机数据，写访问这些地址则会产生一个不确定的影响。用户软件不应将那些没有被列举出来的地址置1。在这种情况下，复位后这些单元数值总是0。定时/计数器2定时/计数器2的控制和状态位位于t2con和t2mod。寄存器对（rcao2h、rcap2l）是定时器2在16位捕获方式或16位自动重装载方式下的捕获/自动重装载寄存器。中断寄存器所有单独的中断允许位都存在于中断允许寄存器ie中。中断优先级寄存器ip可以为六个中断源设置两个中断优先级。数据存储器at89c52实现256字节片上ram。高128个字节与特殊功能寄存器（sfr）地址是重叠的，也就是高128字节的ram和特殊功能寄存器的地址是相同的,但物理上它们是分开的。当一条指令访问7fh 以上的内部地址单元时，指令中使用的寻址方式是不同的，也即寻址方式决定是访问高128 字节ram 还是访问特殊功能寄存器。如果指令是直接寻址方式则为访问特殊功能寄存器。例如，下面的直接寻址指令访问特殊功能寄存器0a0h（即p2 口）地址单元。 mov 0a0h，#data 间接寻址指令访问高128 字节ram，例如，下面的间接寻址指令中，r0 的内容为0a0h，则访问数据字节地址为0a0h，而不是p2 口（0a0h）。 mov r0，#data 堆栈操作也是间接寻址方式，所以，高128 位数据ram 亦可作为堆栈区使用。定时器0/定时器1at89c52的定时器0和定时器1的工作方式与at89c51相同。定时器2定时器2 是一个16位定时/计数器。它既可当定时器使用，也可作为外部事件计数器使用，其工作方式由特殊功能寄存器t2con（如表3）的c/t2位选择。定时器2有三种工作方式：捕获方式，自动重装载（向上或向下计数）方式和波 特率发生器方式，工作方式由t2con的控制位来选择。定时器2由两个8位寄存器th2和tl2组成，在定时器工作方式中，每个机器周期tl2寄存器的值加1，由于一个机器周期由12个振荡时钟构成，因此，计数速率为振荡频率的1/12。rclk +tclkcp/rl2tr2mode00116-bit auto-reload01116-bit capture1x1baud rate generatorxx0(off)在计数工作方式时，当t2引脚上外部输入信号产生由1至0的下降沿时，寄存器的值加1，在这种工作方式下，每个机器周期的5sp2期间，对外部输入进行采样。若在第一个机器周期中采到的值为1，而在下一个机器周期中采到的值为0，则在紧跟着的下一个周期的s3p1期间寄存器加1。由于识别1至0的跳变需要2个机器周期（24个振荡周期），因此，最高计数速率为振荡频率的1/24。为确保采样的正确性，要求输入的电平在变化前至少保持一个完整周期的时间，以保证输入信号至少被采样一次。捕获方式： 在捕获方式下，通过t2con控制位exen2来选择两种方式。如果exen2=0，定时器2是一个16位定时器或计数器，计数溢出时，对t2con的溢出标志tf2置位，同时激活中断。如果exen2=1，定时器2完成相同的操作，而当t2ex引脚外部输入信号发生1至0负跳变时，也出现th2 和tl2 中的值分别被捕获到rcap2h和rcap2l中。另外，t2ex引脚信号的跳变使得t2con中的exf2置位，与tf2相仿，exf2也会激活中断。自动重装载（向上或向下计数器）方式： 当定时器2工作于16位自动重装载方式时，能对其编程为向上或向下计数方式，这个功能可通过特殊功能寄存器t2con的dcen位（允许向下计数）来选择的。复位时，dcen位置“0”，定时器2 默认设置为向上计数。当dcen置位时，定时器2既可向上计数也可向下计数，这取决于t2ex引脚的值。当dcen=0时，定时器2自动设置为向上计数，在这种方式下，t2con 中的exen2 控制位有两种选择，若exen2=0，定时器2为向上计数至0ffffh溢出，置位tf2 激活中断，同时把16 位计数寄存器rcap2h 和rcap2l重装载，rcap2h 和rcap2l 的值可由软件预置。若exen2=1，定时器2的16位重装载由溢出或外部输入端t2ex从1至0的下降沿触发。这个脉冲使exf2置位，如果中断允许，同样产生中断。定时器2 的中断入口地址是：002bh 0032h 。 当dcen=1时，允许定时器2向上或向下计数，如图6所示。这种方式下，t2ex引脚控制计数器方向。t2ex引脚为逻辑“1”时，定时器向上计数，当计数0ffffh向上溢出时，置位tf2，同时把16 位计数寄存器rcap2h和rcap2l重装 载到th2和tl2中。 t2ex引脚为逻辑“0”时，定时器2向下计数，当th2 和tl2中的数值等于rcap2h和rcap2l中的值时，计数溢出，置位tf2，同时将0ffffh数值重新装入定时寄存器中。 当定时/计数器2向上溢出或向下溢出时，置位exf2位。ag an employment tribunal clai emloyment tribunals sort out disagreements between employers and employees. you may need to make a claim to an employment tribunal if: you dont agree with the disciplinary action your employer has taken against you your employer dismisses you and you think that you have been dismissed unfairly. for more informu, take advice from one of the organisations listed underfurther help. employment tribunals are less formal than some other courts, but it is still a legal process and you will need to give evidence under an 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