architecture and circuit design of an all-spintronic fpga

1、Session 1: ArchitectureFPGA18, February 2527,Monterey, CA, USAArchitecture and Circuit Design of an All-Spintronic FPGAStephen M. WilliamsUniversity of Central Florida Department of Electrical and Computer EngineeringOrlando, FL, U.S.A. Stephen.WABSTRACTRecon gurable logic devi

2、ce, such as FPGA, has been well-known tobethe driver ofcutting-edge devicetechnology. In thelast ve years, there have been extensive studies on constructing novel FPGA devices using CMOS technology combined with emerging spin- tronic devices. Unfortunately, although spintronic device technol- ogy pr

3、omises desirable features such as non-volatility and high area density, its relatively slow switching speed makes it quite chal- lenging to use them as drop-in replacements for CMOS transistors. As such, to fully unlock the performance bene ts of spintronic de- vices, it is imperative to develop inn

4、ovative design techniques of circuit and architecture that are custom-made for building high- performance FPGA devices. In this paper, we aim at fully extract- ingthe bene tsofnewspin-baseddevicetechnologythroughinno- vative circuit and architecture design techniques for FPGAs. Specif- ically,we exp

5、loit the uniquecharacteristics ofa domain-walllogic device called the mCell to achieve a direct mapping to NAND-NOR logic and in doing so create a high-throughput non-volatile alter- native to LUT-based CMOS recon gurable logic.To empirically validate our approach, we have performed exten-sive HSpic

6、e circuit simulations. Our simulation results have shown that, for a similar logic capacity, the NAND-NOR FPGA design with mCell devices excels across all metrics when compared to the CMOS NAND-NOR FPGA design. Not only do we reduce average delay by about 17%, but we also improve path delay variance

7、 be- tween di erent logic block con gurations by about 59%, which can ease the burden on the FPGA timing analysis CAD tools by hav- ing more consistent delay between con gurations. To judge the performance of our mCell FPGA in practical applications, we mea- sured it against the Stratix IV LUT-based

8、 FPGA for the MCNC and VTR benchmark suites. Our mCell-based FPGA devices prove to be quite competitive against the CMOS LUT-based FPGA design, on average reducing delay and area by approximately 26% and 64% for the MCNC benchmark, and 13% and 55% for the VTR benchmark respectively.Mingjie LinUniver

9、sity of Central Florida Department of Electrical and Computer EngineeringOrlando, FL, U.S.A. Member, IEEEKEYWORDSSpintronic; FPGA; mCellACM Reference Format:Stephen M. Williams and Mingjie Lin. 2018. Architecture and Circuit De- sign of an All-Spintronic FPGA. In FPGA 18: 2018 ACM/SIGDA Internationa

10、l Symposium on Field-Programmable Gate Arrays, February 2527, 2018, Mon- terey, CA, USA. ACM, New York, NY, USA, 10 pages. /10.1145/3174243.31742561INTRODUCTIONWith Moores law dwindling quickly, the physical limits of CMOS technology make it almost intractable to achieve high energy e

11、- ciency if the traditional logic design methodology still dominates. In fact, a modern FPGA device built with CMOS transistors oper- ating at 0.6V, about 50% of its total energy consumption will be “wasted” as the leakage from idle transistors 17. Therefore, we needto explore new area-energy e cien

12、t device technology and architectures in order to e ectively tackle the upcoming “zettabytes” data explosion in computing. However, between new device tech- nology and the corresponding microarchitecture, which is the best path forward in terms of optimal pairing remains to be unclear. Among many em

13、erging device technologies, spin-based devices, commonly referred to as spintronics, have been shown to be quite promising because they have good scalability, non-volatility, and ultra-low energy 11, all of which may enable fundamental shifts in our computation paradigm that were not possible with C

14、MOS technology. Speci cally, the non-volatility of spintronic devices has the potential to bring massive energy savings in special appli- cations such as normally-o computation 3, 16. Unfortunately, despite many compelling advantages of adopting spintronic de- vices, studies on all-spin logic design

15、s are relatively sparse. In fact, most existing approaches to using spintronic devices often involve amixed-mode usage of CMOS devices, which mayfacechallenges in the fabrication stage. Another bene t of an all-spintronic de- sign is that they are naturally hardened against bit ips due to ra- diatio

16、n 9. As such, it is of great interest to further pursue com- petitive logic circuit design methodologies using only spintronic devices, thus exploiting a more optimized fabrication process and increasing its viability as an alternative to the standard CMOS tech- nology.Among all computing devices, c

17、ontemporary FPGA design, basedon the Look-Up Table (LUT) for logic realization and switch point interconnections for routing, can be a natural candidate for ex- ploring all-spintronic circuit design. Spintronic devices, such as do- main walls and magnetic tunnel junctions, have been used in FPGA arc

18、hitecture research, however it is often used to replace only the con guration SRAM bits as spin-technology has a proven track record for memory 4, 18. Little work has been targeted at the logic block design or the routing interconnections. To our knowl- edge, no existing work has presented an FPGA a

19、rchitecture madeCCS CONCEPTS Hardware Programmable logic elements; Emerging ar- chitectures;Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro t or commercial advantage an

20、d that copies bear this notice and the full cita- tion on the rst page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or re- publish, to post on servers or to redistribute to lists, requires prior speci c per

21、mission and/or a fee. Request permissions from .FPGA 18, February 2527, 2018, Monterey, CA, USA 2018 Association for Computing Machinery. ACM ISBN 978-1-4503-5614-5/18/02. . . $15.00/10.1145/3174243.317425641Session 1: ArchitectureFPGA18, February 2527,Monterey, CA, U

22、SApurely of domain-wall devices. This is not without good reasons. First, spintronic devices, when comparing with the most cutting- edge CMOS technology, have relatively low switching ratio. There- fore, CMOS-based sense ampli ers are used to compensate for the low switching ratios of spin-based dev

23、ices and to aid in fanout. Second, relative to CMOS devices, spintronic devices are also rela- tivelyslow interms ofswitching speed.In modernspintronic digi- tal circuit design, nanosecond range switching delay is considered adequate, though newer spintronic materials have the potential to improve t

24、hat 12. On the device engineering side, faster switch- ing can also be obtained through larger terminal voltages/injec- tion current; however, this can cause excessive heating and device degradation. Ultimately, directly using spintronic devices in the same CMOS circuit design style typically yields

25、 poor results. The best path forward in terms of optimal pairing between new device technology and the corresponding microarchitecture remains un- clear.Despite the above technical challenges, there are several promis-ing opportunities to fully exploit the potential of spintronic devices in construc

26、ting a modern FPGA device. For example, in a modern FPGA device such as a Stratix IV, a complex logic block is com- posed of an 8-input LUT anda multiplexor to choose between reg- istered and sequential output. As a result, as many as 256 6T SRAM bits are required to store the con guration of a sing

27、le logic block. These memory bits incur not only a large area overhead, but an energy and time overhead due to the SRAM needing to be repro- grammed upon each boot cycle, all of which could be better pur- posed as dedicated computation blocks, communication links, or more recon gurable cells. Second

28、, the programming time for an SRAM based Zynq FPGA-SOC can be upwards of 10ms 8, which greatly limits the prospects of dynamic recon gurability for real- time applications such as autonomous vehicle navigation. Third, intermittent power supply also poses an issue as it can interrupt device operation

29、 and cause the con guration to be dropped or lost from the SRAM bits, requiring a lengthy recon guration period. Webelieve that all these issues can be mitigated by adopting non- volatile spintronic devices.Of course, in order to truly unlock the full potential of spintronicdevices in building FPGA

30、devices, simple drop-in device replace- ments is far from enough. To put our work into perspective, in Fig. 1, we present a simple categorization of relevant prior work and our study. Speci cally, our work explores a new frontier of the FPGA microarchitecture design process. We approach the prob- le

31、m from the architectural, logical, and device technology points of view. This provides interesting opportunities to fully extract the bene ts ofnew spin-based technology. Weutilize the unique char- acteristics of domain-wall logic devices to achieve a direct map- ping to NAND-NOR logic and in doing

32、so create a high-throughput non-volatile alternative to LUT-based CMOS recon gurable logic. Overall, our contributions can be summarized as(a)(b)Figure 1: Context of Work. * denotes related work in non- recon gurable logic.(2) Instead of forcing new spintronic devices into the LUT-based FPGA archite

33、cture, we precisely matched the logic block de- sign with the unique device characteristics of spintronic de- vices. As such, we replace the LUT structure with an area- e cient NAND-NOR cone network, interconnect structures based on hardware-e cient MUX-based switching trees, and6T-SRAM con guration

34、 memory bits with 2-mCell non-volatile memory. NAND-NOR is ideal as spintronics can easily im- plement the majority function from which both NAND and NOR can beobtained. Allofthese new circuit design tech- niques are both scalable and exible, and potentially usable for other conic logic structures (

35、AIC, MIG).(3) We have demonstrated through simulations that not only can spintronic devices be used for compact FPGA circuit de- signs, but also can realize delay competitive designs against standard CMOS solutions with the added bene t of non- volatility.The rest of the paper is structured as follo

36、ws: Section 2 brie y describes the physical mechanism of mCell devices and the pros and cons of using mCell devices to construct logic circuits. We then proceed with exploring various circuit architectures to implement FPGA logic blocks in Section 3. In Section 4, we investigate the best circuit des

37、ign techniques to implement various core logic compo- nents within a modern FPGA device, e.g., interconnect structures, con guration bits, and logic block. In particular, we discuss how mCell-based circuit design achieves logic registrations cheaply and naturally, which paves way to ultra- ne micro-

38、pipelining. Finally, in Section 6 and 7, we provide a representative circuit layout and various HSpice simulation results.(1) We have developed various innovative mCell-based circuit design techniques and redesigned all crucial circuit compo- nents in a modern FPGA device including logic block, MUX-

39、 based interconnects, and con guration bits. All of this helps in reducing the fabrication complexity when compared with the hybrid Spin-CMOS FPGA implementations, simply due to the lower number of process stages.42Session 1: ArchitectureFPGA18, February 2527,Monterey, CA, USAmade to use a Giant Spi

40、n Hall E ect (GSHE) write path through a basic change of parameters given above. Domain-wall devices which utilize GSHE switching have been shown to achieve ultra- low energy consumption as low as 100aJ/bit, 100mV terminal volt- age, and switching delay as low as 10ps 12.2.1 Circuit Design using the

41、mCellDespite many advantageous properties spintronic devices have, such as non-volatility and high area density, performing logic circuit design with them turns out to be challenging. In fact, we believe that new circuit design techniques and styles have to be invented in order to fully unleash thei

42、r performance potential. For exam- ple, most work assumes reliable domain wall movement and set- tling points; however, precise domain-wall movement is unreli- able 13. This can lead to errors when temperature, dopant, and geometric variations are inevitably introduced during fabrication. In 6, the

43、authors propose a spintronic logic block. They use the domain-walldevice as a tunable resistance to achieve recon gura- bility, which is hard to achieve given todays spintronic device tech- nology. Their approach relies on auxiliary transistors for core func- tionality, which adds additional fabrica

44、tion stages and will likely create roadblocks to a competitive computation alternative to CMOS transistors. In our work, we use domain-wall devices to create a simple two-state device with reliable transitions between the states as all that is required is full domain-wall movement vs partial move- m

45、ents.Figure 2: 3D view of an mCell domain wall device with STT (Spin Transfer Torque) write path.Device Parameterhold Current DensityMA/cm2Value42200%MTJ Resistance*Area m2 Tunnel Magnetoresistance RatioDomain Wall Depinning Time ps 100Spin PolarizationRead Path Low Resistance Read Path High Resista

46、nce Write Path Resistance Device WidthnmDevice Length nm120%1.25K2.5K1002040Table 1: mCell Device parameter values used in this paper.2THE MCELL, A SPIN-COUPLED DOMAIN-WALL DEVICEAmong many physical realizations of a spintronic device, we fo- cus on those which are based upon domain-wall motion in a

47、 ferro- magnetic nanowire. Typically, such a domain-wall device has elec- trically connected read and write pathways to provides a signal output and to set the domain wall position, respectively. However, this leads to the problem of needing separate read and write phases, along with a few access tr

48、ansistors, further exacerbating the longer delay inherent to spin-devices. In 14, the authors designed a do- main wall device, called the mCell shown in Fig. 2, in which the read and write pathways are electrically isolated. This is achieved by placing a magnetic coupling oxide between two magnetic

49、free layers. Applying a voltage across terminals T1 and T2 causes a spin- polarized current to ow which moves the lower domain wall via spin-transfer torque. This in turn moves the upper domain wall between terminals T3 and T4 via dipolar coupling. Magnetic tun- neling junctions are formed by the ma

50、gnetic materials and oxide at terminals T3 and T4. As the domain wall sweeps from one far end totheother, the resistancebetween T3and T4varies betweenRlow and Rhigh. In our work, we replace the MTJ at terminal T4 with a lower resistance ohmic contact, this further allows for larger cur- rent ow lead

51、ing to faster switching times. Thanks to the isolated read and write paths, the mCell, as well as similar magnetically coupled spin-devices, can be used to design improved spintronic logic circuits. The magnetization state is non-volatile which canaid in achieving lower energy designs. Until now, th

52、e mCell has been only been used in ASIC like designs and not for a full FPGA architecture. Table 1 lists all essential parameters values used to simulate the mCell circuits used in this paper. The model can beFigure 3: mCell bu ercircuit.Shown in Fig. 3 is the core building block of all circuits pre

53、sented in this work. Using two mCells, we create a voltage divider which swings between V+ and V- based on the direction of current ap- plied at the Input terminal. If the current from Input to ground is positive then the output is set to V+, likewise if the current is neg- ative then the output is

54、set to V-. When connected as shown the device acts like a bu er, however if the voltage supply polarity is reversed, then it becomes an inverter. We use this simple bu er-/inverter circuit to create a programmable inverter which has an intrinsically balanced delay. This helps in solving a large part

55、 of the delayvariance inherent in CMOS NAND-NORlogic. Fanout is achieved by connecting a load in series so that each load is driven by the same current. Fanout with mCell devices is energy e cient and uses as little as 1.4fJ in comparison to the 23fJ required by a typical tapered CMOS bu er chain.Th

56、e output current is given in Equation 1(a) where RPU and RPD are the switchable MTJ resistances which range from Rlow and Rhigh, and V/2 is the magnitude of the positive or negative voltage supplies. Gain is provided by increasing the voltage supply43Session 1: ArchitectureFPGA18, February 2527,Mont

57、erey, CA, USAat a given bu ering stage. In our design we use a +/- 65mV terminal voltage for the core logic supplies and +/- 100mV for stages with large fanout. 1 1 +!V11RPURPD , where k = 1 + R output+ I =. (1)2kRPURPD3LOOKUP-TABLE VS NAND-NOR AS BASIS FOR RECONFIGURABLE LOGICWe rethink the entire

58、FPGA design from the ground up by rst ex- amining the the most fundamental circuit component of an FPGA devicethe logic blocks. It is well-known that, with the CMOS de- vice technology, the LUT-based logic block architecture has long been dominant. However, this traditional LUT circuit design re- qu

59、ires many multiplexors, in which the area and delay scale al- most exponentially and logarithmically as the number of inputs increases. Unfortunately, directly duplicating such an LUT-based circuit design with delay-constrained spin-devices incurs technical issues such as excessive delay and path design imbalance. Further- more, w