VHDL洗衣机设计

1、eda课程实训报告一、实训课题：洗衣机控制器的设计二、设计的内容及要求：1设计一个洗衣机控制器，要求为：1) 洗衣机控制器可以驱动洗衣机进行洗涤、漂洗或烘干；2) 洗衣机控制器可以设置洗衣机的工作时间，工作时间最短1分钟，最长30分钟，在工作过程中，工作时间以倒计时显示，若时间为0洗衣机停止工作；3) 洗衣机在待机状态时，洗衣机控制器可以设置洗衣机的工作方式和工作时间；4) 可以暂停或停止洗衣机工作；5) 利用四个数码管显示洗衣机待机时的设置时间和工作时的运行时间，利用一位数码管显示洗衣机待机时所设置的工作方式运行时的工作方式；6）利用三个led分别表示驱动洗衣机进行洗涤、漂洗或烘干。2洗衣机

2、控制器可以划分为状态机模块、计时器模块、设置模块和显示选择模块。在quartusii中输入各个模块的代码，编译综合，仿真，完成各个模块的软件设计；4把各个模块组合起来，综合编译，仿真，完成整个交通灯控制器系统的软件设计；5. 选择电路方案锁定管脚，把程序下载到实验箱中，利用实验箱进行硬件实现；6. 完成实训报告。实训报告包括：1) 设计的任务和要求；2) 模块的划分和系统总框图；3) 各个模块的实现，包括模块的作用，模块的输入与输出情况，模块状态图，模块的代码以及注释，模块的波形图；4) 系统的实现，包括系统总原理图，系统的波形图；5) 管脚的锁定关系；三设计思路：u 状态切换有限状态机u 按

3、定时时间及时 定时计数器u 显示时间 数码管译码驱动器u 接收设置时间时间设置键盘扫描器u 接收设置模式 模式设置键盘扫描器u 切换显示运行时间和设置时间二路选择器u 切换显示运行模式和设置模式二路选择器整体设计示意图：四系统组成以及系统各部分的设计： 1.状态机的设计： 状态机要完成的功能：l 能设置工作模式；l 控制洗涤、漂洗、干衣的驱动输出；l 能启动、暂停、停止洗衣机控制器；l 能重启、暂停和停止定时器；l 能接收定时器的到时标志；l 能使能键盘扫描计数器；l 能控制二路选择器。 状态图分析设计如下： 模块设计图如下：状态机仿真图如下：2. 定时器设计：定时器的功能：l 能通过使能端暂

4、停和允许定时器工作；l 能停止并复位定时器；l 能进行定时；l 能输出定时标志 模块设计图如下： 定时器波形图如下： 3.时间设置： 时间设置键盘扫描器的功能：l 能响应按键；l 能在使能端的控制下工作 模式设计图如下： 波形图如下： 4.模式设置: 模式设置键盘扫描器的功能：预设工作模式，”000”为待机，”001”为洗涤，”010”为漂洗，”022”为干衣，”100”为暂停模式设计图如下：波形图如下： 5. 二路选择器 二路选择器的功能：设置显示运行时间还是设置时间，显示运行模式还是设置模式。模式设计图如下：整体结构图：整体波形图：五下载时选择的开发系统模式以及管脚1.管教配置：2. 实验

5、电路结构图：附录代码：1.状态机library ieee;use ieee.std_logic_1164.all;entity shell_washmachine isport (clk,modein0,modein1,modein2,pause,start,stop,tcin: in std_logic;ken,modeout0,modeout1,modeout2,sel,ten,tstop,wout0,wout1,wout2 : out std_logic);end;architecture behavior of shell_washmachine istype type_sreg is

6、 (dry,ready,rinse,waitup,wash);signal sreg, next_sreg : type_sreg;signal next_ken,next_modeout0,next_modeout1,next_modeout2,next_sel,next_ten,next_tstop,next_wout0,next_wout1,next_wout2 : std_logic;signal modeout : std_logic_vector (2 downto 0);signal wout : std_logic_vector (2 downto 0);beginproces

7、s (clk, stop, next_sreg, next_ken, next_sel, next_ten, next_tstop, next_modeout2, next_modeout1, next_modeout0, next_wout2, next_wout1, next_wout0)beginif ( stop=1 ) thensreg = ready;sel = 0;ken = 1;ten = 1;tstop = 1;modeout2 = 0;modeout1 = 0;modeout0 = 0;wout2 = 0;wout1 = 0;wout0 = 0;elsif clk=1 an

8、d clkevent thensreg = next_sreg;ken = next_ken;sel = next_sel;ten = next_ten;tstop = next_tstop;modeout2 = next_modeout2;modeout1 = next_modeout1;modeout0 = next_modeout0;wout2 = next_wout2;wout1 = next_wout1;wout0 = next_wout0;end if;end process;process (sreg,modein0,modein1,modein2,pause,start,tci

9、n,modeout,wout)beginnext_ken = 0; next_modeout0 = 0; next_modeout1 = 0; next_modeout2 = 0; next_sel = 0; next_ten = 0; next_tstop = 0; next_wout0 = 0; next_wout1 = 0; next_wout2 = 0; modeout=std_logic_vector(000); wout=std_logic_vector(000); next_sregif ( pause=0 and tcin=0 ) thennext_sreg=dry;next_

10、ten=1;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(011);wout = (std_logic_vector(100);end if;if ( tcin=0 and pause=1 ) thennext_sreg=waitup;next_ten=0;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(100);wout = (std_logic_vector(000);end if;if ( tcin=1 ) thennext_sre

11、g=ready;next_ten=1;next_tstop=1;next_ken=1;next_sel=0;modeout = (std_logic_vector(000);wout if ( modein1=0 and modein0=0 ) or ( modein2=1 ) or ( start=0 ) thennext_sreg=ready;next_ten=1;next_tstop=1;next_ken=1;next_sel=0;modeout = (std_logic_vector(000);wout = (std_logic_vector(000);end if;if ( mode

12、in0=1 and modein1=1 and modein2=0 and start=1 ) thennext_sreg=dry;next_ten=1;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(011);wout = (std_logic_vector(100);end if;if ( modein0=0 and modein1=1 and modein2=0 and start=1 ) thennext_sreg=rinse;next_ten=1;next_tstop=0;next_ken=0;next_s

13、el=1;modeout = (std_logic_vector(010);wout = (std_logic_vector(010);end if;if ( modein0=1 and modein1=0 and modein2=0 and start=1 ) thennext_sreg=wash;next_ten=1;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(001);wout if ( pause=0 and tcin=0 ) thennext_sreg=rinse;next_ten=1;next_tst

14、op=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(010);wout = (std_logic_vector(010);end if;if ( tcin=0 and pause=1 ) thennext_sreg=waitup;next_ten=0;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(100);wout = (std_logic_vector(000);end if;if ( tcin=1 ) thennext_sreg=ready;next_t

15、en=1;next_tstop=1;next_ken=1;next_sel=0;modeout = (std_logic_vector(000);wout if ( modein1=0 and modein0=0 ) or ( modein2=1 ) or ( pause=1 ) thennext_sreg=waitup;next_ten=0;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(100);wout = (std_logic_vector(000);end if;if ( modein0=1 and mod

16、ein1=1 and modein2=0 and pause=0 ) thennext_sreg=dry;next_ten=1;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(011);wout = (std_logic_vector(100);end if;if ( modein0=0 and modein1=1 and modein2=0 and pause=0 ) thennext_sreg=rinse;next_ten=1;next_tstop=0;next_ken=0;next_sel=1;modeout

17、= (std_logic_vector(010);wout = (std_logic_vector(010);end if;if ( modein0=1 and modein1=0 and modein2=0 and pause=0 ) thennext_sreg=wash;next_ten=1;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(001);wout if ( pause=0 and tcin=0 ) thennext_sreg=wash;next_ten=1;next_tstop=0;next_ken=

18、0;next_sel=1;modeout = (std_logic_vector(001);wout = (std_logic_vector(001);end if;if ( tcin=0 and pause=1 ) thennext_sreg=waitup;next_ten=0;next_tstop=0;next_ken=0;next_sel=1;modeout = (std_logic_vector(100);wout = (std_logic_vector(000);end if;if ( tcin=1 ) thennext_sreg=ready;next_ten=1;next_tsto

19、p=1;next_ken=1;next_sel=0;modeout = (std_logic_vector(000);wout end case;next_modeout2 = modeout(2);next_modeout1 = modeout(1);next_modeout0 = modeout(0);next_wout2 = wout(2);next_wout1 = wout(1);next_wout0 clk,modein0=modein(0),modein1=modein(1),modein2=modein(2),pause=pause,start=start,stop=stop,t

20、cin=tcin,ken=ken,modeout0=modeout(0),modeout1=modeout(1),modeout2=modeout(2),sel=sel,ten=ten,tstop=tstop,wout0=wout(0),wout1=wout(1),wout2=wout(2);end behavior; 2 定时器： library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dingshi is port(clk,ten,tstop:in std_logic; ims:in s

21、td_logic_vector(3 downto 0); iss:in std_logic_vector(3 downto 0); img:in std_logic_vector(3 downto 0); isg:in std_logic_vector(3 downto 0); cin:out std_logic; omg, osg:buffer std_logic_vector(3 downto 0); oms:buffer std_logic_vector(3 downto 0); oss:buffer std_logic_vector(3 downto 0) ); end; archit

22、ecture cml of dingshi isbegin process(clk, ten, tstop) begin if ten=1 then if tstop=1 then osg0000 or omg0000 or oms0000 then osg=1001; else osg=0000; end if; else osg=osg-1; end if; end if; end if; end process; process(clk, ten, tstop, osg) begin if ten=1 then if tstop=1 then oss0000 or oms0000 the

23、n oss=0101; else oss=0000; end if; else oss=oss-1; end if; end if; end if; end if; end process; process(clk, ten, tstop, osg, oss) begin if ten=1 then if tstop=1 then omg0 then omg=1001; else omg=0000; end if; else omg=omg-1; end if; end if; end if; end if; end process; process(clk, ten, tstop, osg,

24、 oss, omg) begin if ten=1 then if tstop=1 then oms=ims; elsif clkevent and clk=1 then if omg=0 and osg=0 and oss=0 then if oms=0 then oms=0000; else oms=oms-1; end if; end if; end if; end if; end process; process(clk, ten, tstop, osg, oss, omg, oms) begin if ten=1 then if tstop=0 then if clkevent an

25、d clk=1 then if oms=0 and omg=0 and oss=0 and osg=1 then cin=1; else cin=0; end if; end if; end if; end if; end process; end cml; 3.时间设置：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key isport( kin: in std_logic; ken: in std_logic; ims,iss,img,isg: buffer std_logic

26、_vector(3 downto 0); end key;architecture cml of key isbegin process(kin, ken) begin if ken=1 then if kinevent and kin=1 then if isg=1001 then isg=0000; else isg=isg+1; end if; end if; end if; end process; process(kin, ken, isg) begin if ken=1 then if kinevent and kin=1 then if isg=9 then if iss=010

27、1 then iss=0000; else iss=iss+1; end if; end if; end if; end if; end process; process(kin, ken, isg, iss) begin if ken=1 then if kinevent and kin=1 then if iss=0101 and isg=1001 then if img=1001 then img=0000; else img=img+1; end if; end if; end if; end if; end process; process(kin, ken, isg, iss, i

28、mg) begin if ken=1 then if kinevent and kin=1 then if img=1001 and iss=0101 and isg=1001 then if ims=0010 then ims=0000; else ims=ims+1; end if; end if; end if; end if; end process; end cml;4.模式设置：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mode isport(kin :in std

29、_logic;ken :in std_logic;modeset:buffer std_logic_vector(2 downto 0);led:out std_logic_vector(2 downto 0);end mode;architecture cml of mode issignal a: std_logic_vector(2 downto 0);signal k: std_logic;beginprocess(kin,ken) beginif ken=1 then if rising_edge(kin) then if a=100 thena=000;elsea=a+1;end if;end if;end if;end process;modesetledledledled=00