2010年吉林高考语文试题.ppt

1、在系统可编程技术,第14讲 VHDL语言语言时序逻辑电路设计,时钟的描述方法,上升沿：CPEVENT AND CP=1,下升沿：CPEVENT AND CP=0,上升沿D触发器描述,方法一：使用信号属性函数,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS(CP) BEGIN IF (CPEVENT AND CP=1) THEN Q=D

2、; END PROCESS; END test;,方法二：使用WAIT 语句,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS BEGIN WAIT UNTIL CP=1; Q=D; END PROCESS; END test;,上升沿D触发器描述,方法三：使用上升沿检测函数,LIBRARY IEEE; USE IEEE.STD_LOG

3、IC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS(cp) BEGIN IF (rising_edge(cp) THEN Q=D; END IF; END PROCESS; END test;,上升沿D触发器描述,方法四：使用进程的启动特性,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOG

4、IC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS（CP） BEGIN IF CP=1 THEN Q=D; END IF; END PROCESS; END test;,上升沿D触发器描述,上升沿D触发器描述,下降沿D触发器描述,方法一：使用信号属性函数,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECT

5、URE test OF D_reg IS BEGIN PROCESS(CP) BEGIN IF (CPEVENT AND CP=0) THEN Q=D; END PROCESS; END test;,方法二：使用WAIT 语句,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS BEGIN WAIT UNTIL CP=0; Q=D; EN

6、D PROCESS; END test;,下降沿D触发器描述,方法三：使用下降沿检测函数,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS(cp) BEGIN IF (falling_edge(cp) THEN Q=D; END IF; END PROCESS; END test;,下降沿D触发器描述,方法四：使用进程的启动特性,LIB

7、RARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS（CP） BEGIN IF CP=0 THEN Q=D; END IF; END PROCESS; END test;,下降沿D触发器描述,下降沿D触发器描述,髙电平D触发器描述,方法：使用进程的启动特性,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; EN

8、TITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS（CP，D） BEGIN IF CP=1 THEN Q=D; END IF; END PROCESS; END test;,髙电平D触发器描述,低电平D触发器描述,方法：使用进程的启动特性,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LO

9、GIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS（CP，D） BEGIN IF CP=0 THEN Q=D; END IF; END PROCESS; END test;,低电平D触发器描述,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(d,clk,clr:IN STD_LOGIC; q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS (clk, c

10、lr) BEGIN IF clr = 1 THEN q = 0; ELSIF clkEVENT AND clk = 1 THEN q = d; END IF; END PROCESS; END test;,异步复位D触发器,异步复位D触发器,ARCHITECTURE test OF D_reg IS BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk = 1 THEN IF clr = 1 THEN q = 0; ELSE q = d; END IF; END IF; END PROCESS; END test;,同步复位D触发器,同步复位D触发器,例：

11、设计一异步清零、同步置数的同步8421BCD码计数器,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT10 IS PORT(CLK,R,S:IN STD_LOGIC; DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC; Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); END COUNT10;,时序电路设计举例,ARCHITECTURE test OF COUNT10 IS BEGIN CO=1 WHEN (Q=1001) ELSE 0; PROCESS(CLK,R)