jetson 系列移植指南 Jetson-Xavier-NX-and-Jetson-Nano-Interface-Comparison-Migration-Application-Note-v1.0

DA-09761-001_v1.0|April2020

NVIDIAJetsonXavierNXandJetsonNanoInterfaceComparisonandMigration

ApplicationNote

NVIDIAJetsonXavierNXandJetsonNanoInterfaceComparisonandMigration

DA-09761-001_v1.0|

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DocumentHistory

DA-09761-001_v1.0

Version

Date

DescriptionofChange

0.5

December12,2019

PreliminaryInformation

1.0

April20,2020

Update

Figure1

and

Figure2

Updated

Table1

Addednoteregardingimagesfor

Figure3

and

Figure4

Updated

Table3

toreflectchangeoflanesusedforPCIeinlatestJetsonXavierNXmoduledesign

Updated“

PCIExpress

”section

Updated“

Camera

”section

TableofContents

NVIDIAJetsonXavierNXandJetsonNanoInterfaceComparisonandMigration

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Introduction 1

JetsonXavierNXvs.JetsonNano 2

ModuleInterfaceComparisons 4

FunctionandInterfaceDifferenceDetails 6

MechanicalDifferences 6

USB3.xandPCIExpressMapping 7

PCIExpress 8

Display 9

DSI 9

eDP,DP,andHDMI 10

CAN 10

Camera 10

Debug 11

ListofFigures

NVIDIAJetsonXavierNXandJetsonNanoInterfaceComparisonandMigration

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Figure1. JetsonNanoBlockDiagram 2

Figure2. JetsonXavierNXBlockDiagram 3

Figure3. JetsonNanovs.JetsonXavierNXModuleTop 6

Figure4. JetsonNanovs.JetsonXavierNXModuleBottom 7

Figure5. JetsonXavierNXandJetsonNanoPCIeBlockDiagram 9

Figure6. JetsonNanoDSIBlockDiagram 9

Figure7. JetsonXavierNXCANBlockDiagram 10

Figure8. JetsonXavierNXandJetsonNanoCSIBlockDiagrams 11

ListofTables

Table1. JetsonXavierandJetsonNanoFeatureComparison 4

Table2. MechanicalDifferences 6

Table3. JetsonXavierNXUSB3.1andPCIeLaneMappingConfigurations 7

Table4. JetsonNanoUSB3.0andPCIeLaneMappingConfigurations 8

Table5. eDP,DP,andHDMIDisplaySupport 10

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Introduction

ThisapplicationnotecomparesthefeaturesandinterfacessupportedontheNVIDIA®JetsonXavier™NXandJetsonNano™modules.ThisapplicationnotealsodescribesthemigrationpathfordesignersfamiliarwithJetsonNanotodesignacarrierboardforJetsonXavierNXthatwillsupportthefeaturesavailableonJetsonXavierNX.

JetsonXavierNXvs.JetsonNano

TheJetsonXavierNXandJetsonNanomodulesarepincompatiblewithafewexceptions.ThisapplicationnotedescribesthedifferencestoallowusersfamiliarwithJetsonNanotodesignasimilarcarrierboardforJetsonXavierNX.

ThefollowingfiguresshowtheJetsonXavierNXandJetsonNanoblockdiagrams.Theinterfacesorblocksthataresupportedonlybyoneofthemodulesarehighlightedinred.Theinterfacetypesthataresupportedonbothmodulesbutwherethenumberoflanes/instances,voltagelevel,oraccessisdifferentarehighlightedinmagenta.

Figure1. JetsonNanoBlockDiagram

LPDDR4

4GB

GigabitEthernet

eMMC16GB

Power

Subsystem

CPU/GPU&CoreRegs

Power&VoltageMonitors

GeneralPurpose

Clocks2x

PWM3x

CAMMCLKx2

UARTx3

CSI:3x4or4x2

SPI1x2

HPDx2,CEC

I2Sx2

DP_AUX/DDC

AUDIOMCLK

DP/HDMI

I2Cx3–3.3V

eDP/DP

I2Cx1–1.8V

DSI,2-lanex1

SDCARD/SDIO

PCIex4

PMIC

GBE_MDI

USB3.0x1

USB2.0x3

VDD_IN

JetsonNano

TegraX1

JTAGTestPoints

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JetsonXavierNXvs.JetsonNano

tsonXavierNX

PowerSubsystem

PMIC

CPU/GPU&CoreRegsPower&Voltage

Monitors

PWM3x

GeneralPurpose

Clocks2x

CAMMCLK2x

CSI:3x4or6x2

HPD2x,CEC

DP_AUX/DDC2x

[E]DP/HDMI2x

PCIex1+x4

USB3.11x

USB2.03x

Xavier

Figure2. JetsonXavierNXBlockDiagram

Je

VDD_IN

GBE_MDI

SDCARD/SDIO

I2C1x–1.8V

I2C3x–3.3V

AUDIOMCLK

I2S2x

DIGITALMIC

SPI2x

UART3x

CAN1x

LPDDR4x8GB

GigabitEthernet

QSPINOR32MB

eMMC16GB

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ModuleInterfaceComparisons

Table1

liststhekeysystemspecifications,devicesandinterfacesthataresupportedoneithertheJetsonXavierNXortheJetsonNanomodule.

Table1. JetsonXavierandJetsonNanoFeatureComparison

Feature

JetsonXavierNX

JetsonNano

SystemSpecificationsandDeviceontheModule

GPU

NVIDIAVolta™architecturewith384NVIDIA®CUDA®coresand48Tensorcores

NVIDIAMaxwell™architecturewith128CUDAcores

CPU

6-coreNVIDIACarmelArmv8.264-bitCPU

Quad-coreARMCortex-A57MPCoreprocessor

DLAccelerator

2xNVDLAEngines

Notsupported

VisionAccelerator

7-WayVLIWVisionProcessor

Notsupported

Memory

8GB128-bitLPDDR4x

4GB64-bitLPDDR4

Storage

16GBeMMC

Networking

10/100/1000Mbit

VideoEncode

2x464MP/sec

250MP/sec

2x4K@30(HEVC)

1x4K@30(HEVC)

6x1080p@60(HEVC)

2x1080p@60(HEVC)

14x1080p@30(HEVC)

4x1080p@30(HEVC)

4x720p@60(HEVC)

9x720p@30(HEVC)

VideoDecode

2x690MP/sec

500MP/sec

2x4K@60(HEVC)

1x4K@60(HEVC)

4x4K@30(HEVC)

2x4K@30(HEVC)

12x1080p@60(HEVC)

4x1080p@60(HEVC)

32x1080p@30(HEVC)

8x1080p@30(HEVC)

16x1080p@30(H.264)

9x720p@60(HEVC)

Camera

14lanes(3x4or6x2)MIPICSI-2D-PHY

1.2(2.5Gb/sperpair)

12lanes(3x4or4x2)MIPICSI-2D-PHY

1.1(1.5Gb/sperpair)

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ModuleInterfaceComparisons

Feature

JetsonXavierNX

JetsonNano

SystemSpecificationsandDeviceontheModule

Mechanical

69.6mmx45mm260-pinedgeconnector

InputVoltage

5V(nominal)

Interfaces

USB2.0

3x

USB3.x

1x(3.1GEN2)

1x(3.0GEN1)

PCIe

1x1(Gen3)+1x4(Gen4).x1isRootPortonly.x4hasbothRootPortandEndpoint

support

1x4(Gen2),RootPortonly.

Display

Twomulti-mode(e)DP1.4/HDMI™2.0a

HDMI2.0orDP1.2,eDP1.4

DSI(1x2)

Audio(I2S)

2x

SDIO/SDCard

1xSDCard/SDIO

I2C

4x

CAN

1x

Notsupported

UART

3x

SPI

2x

JTAG

Notsupported

Broughttoon-moduletestpointsonly

Fan

PWMandTachInput

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FunctionandInterfaceDifferenceDetails

MechanicalDifferences

Table2

liststhemechanicaldifferences.

Table2. MechanicalDifferences

Feature

JetsonXavierNX

JetsonNano

Size

69.5mmx45mm

Built-inthermalsolution

None

Thermalsolutionmounting

4holesinPCBformountingthermalsolutiontoJetsonXavierNX.

SameapproachasJetsonXavierNXexceptthatthethermalsolutionmountinghole

locationsaredifferent.

Figure3. JetsonNanovs.JetsonXavierNXModuleTop

45mm

69.5mm

45mm

69.5mm

JetsonXavierNXTop JetsonNanoTop

FunctionandInterfaceDifferenceDetails

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Figure4. JetsonNanovs.JetsonXavierNXModuleBottom

JetsonXavierNXBottom

JetsonNanoBottom

Note:Imagesin

Figure3

and

Figure4

aretakenfromthe3DCADSTEPmodelswhichshowonlythe“envelop”viewwhichprovidesthemaximumcomponentheightsbyregioninsteadoftheindividualcomponents.Seethethermaldesignguidesformoredetailedimagesofthemodule.

USB3.xandPCIExpressMapping

ThefollowingtablesshowthedifferentoptionsformappingUSB3.xandPCIetothecommonsetofinterfacepins.

Table3. JetsonXavierNXUSB3.1andPCIeLaneMappingConfigurations

JetsonXavierNXPinNames

PCIE0_RX3PCIE0_TX3

PCIE0_RX2PCIE0_TX2

PCIE0_RX1PCIE0_TX1

PCIE0_RX0PCIE0_TX0

PCIE1_RX0PCIE1_TX0

USBSS_RXUSBSS_TX

XavierLanes

NVHSLane3

NVHSLane2

NVHSLane1

NVHSLane0

PCIeLane11

Lane1

USB3.1

PCIe

1

1x4+1x1

PCIe0lane3

(Ctrl#5)

PCIe0lane2

(Ctrl#5)

PCIe0lane1

(Ctrl#5)

PCIe0lane0

(Ctrl#5)

PCIe1lane0

(Ctrl#4)

USB_SS

Port#2

RecommendedUsage

PCIex4connectorordevice(i.e.M.2KeyM)

PCIex1conn.ordevice(i.e.M.2KeyE)

USB3.1

connector,deviceorhub

Table4. JetsonNanoUSB3.0andPCIeLaneMappingConfigurations

JetsonNanoPinNames

na

PCIE0_RX3PCIE0_TX3

PCIE0_RX2PCIE0_TX2

PCIE0_RX1PCIE0_TX1

PCIE1_RX0PCIE1_TX0

USBSS_RXUSBSS_TX

NVIDIATegraX1Lanes

Lane0

Lane1

Lane2

Lane3

Lane4

Lane6

USB3.0

PCIe

1

1x4

PCIe1lane0–Usedon-moduleforEthernet

PCIe0lane3

(Ctrl#0)

PCIe0lane2

(Ctrl#0)

PCIe0lane1

(Ctrl#0)

PCIe0lane0

(Ctrl#0)

USB_SS

Port#0

UsageonNVIDIADevKitCarrierBoard

Ethernet

Unused

M.2KeyE

USB3.0TypeA

PCIExpress

JetsonXavierNXsupportstwoPCIeinterfaces:Ax1laneinterfaceandax4laneinterface(canbex2orx1instead)atthemodulepins.JetsonNanosupportsonlythex4laneinterface(canbex2orx1instead).atthemodulepins.JetsonXavierNXsupportsbothRootPortandEndpointoperationonthex4interfaceuptoGen4.Thex1interfacesupportsonlyRootPortandonlyuptoGen3.JetsonNanoonlysupportsRootPortoperationuptoGen2.

Figure5. JetsonXavierNXandJetsonNanoPCIeBlockDiagram

Jetson

Nano

PCIE0_TX3_N

PCIE0_TX3_P

156

154

PCIE0_RX3_N155

PCIE0_RX3_P157

PCIE0_TX2_N 148

PCIE0_TX2_P 150

PCIE0_RX2_N 149

PCIE0_RX2_P 151

PCIE0_TX1_N 140

PCIE0_TX1_P 142

PCIE0_RX1_N 137

PCIE0_RX1_P 139

PCIE0_TX0_N 134

PCIE0_TX0_P 136

PCIE0_RX0_N 133

PCIE0_RX0_P 137

PCIE0_CLK_N 160

PCIE0_CLK_P 162

PCIE0_CLKREQ* 180

PCIE0_RST* 181

PCIE_WAKE*

179

0.1uF

0.1uF

PCIe0Lane3

0.1uF

0.1uF

PCIe0Lane2

0.1uF

0.1uF

PCIe0Lane1

0.1uF

0.1uF

PCIe0Lane0

JetsonXavierNX

PCIE0_TX3_N 156

0.22uF

PCIE0_TX3_P

PCIE0_RX3_NPCIE0_RX3_P

0.22uF

154

155

157

PCIe0Lane3

PCIE0_TX2_N

148

0.22uF

UnusedonCarrierBoard

PCIE0_TX2_P

PCIE0_RX2_NPCIE0_RX2_P

0.22uF

150

149

151

PCIe0Lane2

PCIE0_TX1_N

140

0.22uF

PCIe0(Ctrl#5)–PCIex4

PCIE0_TX1_P

PCIE0_RX1_NPCIE0_RX1_P

0.22uF

142

137

139

PCIe0Lane1

conn/device(i.e.M.2KeyM)

PCIE0_TX0_N

134

0.22uF

PCIe0(Ctrl#0)Lane0–RoutedtoM.2KeyEConnectoronCarrierBoard

NVHS0_REFCLK

PCIE0_TX0_P

Mux

SEL

PCIE0_RX0_NPCIE0_RX0_P

PCIE0_CLK_NPCIE0_CLK_P

0.22uF

136

133

137

160

162

PCIe0Lane0

PEX_CLK5

CAN0_EN

PCIE1_TX0_NPCIE1_TX0_P

0.22uF

134

0.22uF

136

PCIE1_RX0_NPCIE1_RX0_P

PCIE1_CLK_NPCIE1_CLK_P

PCIE1_CLKREQ*PCIE1_RST*

PCIE_WAKE*

PCIE0_CLKREQ*PCIE0_RST*

133

137

160

162

180

181

179

180

181

PCIe1Lane0PCIe1(Ctrl#4)–PCIex1

conn/device(i.e.M.2KeyE)

PCIe1(Ctrl#4)–PCIex1conn/device(i.e.M.2KeyE)

Sharedwakepin

PCIe0(Ctrl#5)–PCIex4conn/device(i.e.M.2KeyM)

Display

JetsonNanosupportsDSI,Vesa®DisplayPort™(DP),embeddedDisplayPort(eDP),andHDMIasdescribedinthissection.JetsonXavierNXdoesnotsupportDSIbutdoessupportDisplayPort(DP),embeddedDisplayPort(eDP),andHDMIwithsomedifferences.

DSI

JetsonXavierNXdoesnotsupportDSI.JetsonNanosupportsasingle2-laneDSIinterface.

Figure6. JetsonNanoDSIBlockDiagram

JetsonNano

DSI_CLK_P

DSI_CLK_NDSI_D0_PDSI_D0_NDSI_D1_PDSI_D1_N

78

76

72

70

84

82

DisplayConn.(DSI)

A_CLKP

A_CLKN

A_D0P

A_D0N

A_D1P

A_D1N

eDP,DP,andHDMI

BothJetsonXavierNXandJetsonNanocansupporteDP,DP,andHDMIdisplays.JetsonXavierNXcansupportanyofthesedisplaysoneitherofthetwointerfaces.JetsonNanohasoneinterfacethatsupportsonlyeDP(orDP-displayonly)whiletheothersupportsHDMI,eDP,orDP.

Table5. eDP,DP,andHDMIDisplaySupport

Feature

JetsonXavierNX

JetsonNano

eDP/DP

DP[1:0]_TXD[3:0]_P/N,DP[1:0]_AUX_P/N,DP[1:0]_HPD

DP0_TXD[3:0]_P/N,DP0_AUX_P/N,DP0_HPD

HDMI/DP

DP1_TXD[3:0]_P/N,DP1_AUX_P/N,DP1_HPD,HDMI_CEC

CAN

JetsonXavierNXsupportsasingleCANinterface.JetsonNanodoesnotsupportCAN.

Figure7. JetsonXavierNXCANBlockDiagram

JetsonXavierNX

CAN_TXCAN_RX

143

145

CANPHY

Camera

JetsonNanohas12CSIdatalanes.JetsonXavierNXhas14totaldatalanesalthoughonly12canbeusedinadesign.JetsonXavierNXandJetsonNanosupportthefollowingconfigurationstocamerasorserializers:

⯈JetsonXavierNX

3x4,2x4+2x2,1x4+4x2,or6x2

⯈JetsonNano

3x4,2x4+2x2,1x4+3x2,or4x2

Figure8. JetsonXavierNXandJetsonNanoCSIBlockDiagrams

52

54

46

48

58

60

40

42

64

66

CSI_4_CLK_NCSI_4_CLK_PCSI_4_D0_NCSI_4_D0_PCSI_4_D1_NCSI_4_D1_PCSI_4_D2_NCSI_4_D2_PCSI_4_D3_N

CSI_4_D3_P

27

29

21

23

33

35

CSI_3_CLK_NCSI_3_CLK_PCSI_3_D0_NCSI_3_D0_PCSI_3_D1_N

CSI_3_D1_P

CSI_2_CLK_N 28

CSI_2_CLK_P 30

CSI_2_D0_N 22

CSI_2_D0_P 24

CSI_2_D1_N 34

CSI_2_D1_P 36

JetsonNano

CSI_0_CLK_N 10

CSI_0_CLK_P 12

CSI_0_D0_N 4

CSI_0_D0_P 6

CSI_0_D1_N 16

CSI_0_D1_P 18

CSI_1_D0_N 3

CSI_1_D0_P 5

CSI_1_D1_N 15

CSI_1_D1_P 17

Camera0(2-Lane)

Camera0/1(4-Lane)OnlyCSI0ClockUsed

Camera1(2-Lane)

CSI1_CLK_N 9

CSI1_CLK_P 11

CSI1_D0_N 3

CSI1_D0_P 5

CSI1_D1_N 15

CSI1_D1_P 17

CSI2_CLK_N 28

CSI2_CLK_P 30

CSI2_D0_N 22

CSI2_D0_P 24

CSI2_D1_N 34

CSI2_D1_P 36

CSI3_CLK_N 27

CSI3_CLK_P 29

CSI3_D0_N 21

CSI3_D0_P 23

CSI3_D1_N 33

CSI3_D1_P 35

CSI4_CLK_N 52

CSI4_CLK_P 54

CSI4_D0_N 46

CSI4_D0_P 48

CSI4_D1_N 58

CSI4_D1_P 60

CSI4_D2_N 40

CSI4_D2_P 42

CSI4_D3_N 64

CSI4_D3_P 66

DSI_CLK_N 76

DSI_CLK_P 78

DSI_D0_N 70

DSI_D0_P 72

DSI_D1_N 82

DSI_D1_P 84

10

12

4

6

16

18

CSI_0_CLK_NCSI_0_CLK_PCSI_0_D0_NCSI_0_D0_PCSI_0_D1_N

CSI_0_D1_P

NX

JetsonXavier

Camera2(2-Lane)

Camera1(4-Lane)OnlyCSI0ClockUsed

Camera2(2-Lane)

Camera3(2-Lane)

Camera2/3(4-Lane)OnlyCSI2ClockUsed

Camera3(2-Lane)

Camera4(2-Lane)

Camera2(4-Lane)OnlyCSI2ClockUsed

Camera4(2-Lane)

Camera4

(1,2,or4-Lane)

Camera5(2-Lane)

Camera3(4-Lane)

Camera6(2-Lane)

Debug

JetsonNanobringstheJTAGinterfacetotestpointsonthemoduleonly.JetsonXavierNXdoesnotsupportJTAG.BothJetsonNanoandJetsonXavierNXprovideUART2fordebugpurposes.

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