用在HCL中表示指令

SEQCPUImplementationWhatwewilldiscusstoday?TheimplementationofasequentialCPU----SEQEveryInstructionfinishedinonecycle.InstructionexecutesinsequentialNotwoinstructionexecuteinparalleloroverlapAnrevisedversionofSEQ----SEQ+ModifythePCUpdatestageofSEQtoshowthedifferencebetweenISAandimplementationSomeMacrosNameValueMeaningINOP0CodefornopinstructionIHALT1CodeforhaltinstructionIRRMOVL2CodeforrrmovlinstructionIIRMOVL3CodeforirmovlinstructionIRMMOVL4CodeforrmmovlinstructionIMRMOVL5CodeformrmovlinstructionIOPL6CodeforintegeropinstructionsIJXX7Codeforjumpinstructions……………………………IPOPLBCodeforpoplinstructionRESPRENONE68RegisterIDfor%espIndicatesnoregisterfileaccessALUADD0FunctionforadditionoperationInstructionmemoryInstructionmemoryPCincrementPCincrementCCCCALUALUDatamemoryDatamemoryFetchDecodeExecuteMemoryWritebackicode,ifunrA,rBvalCRegisterfileRegisterfileABMERegisterfileRegisterfileABMEPCvalPsrcA,srcBdstA,dstBvalA,valBaluA,aluBBchvalEAddr,DatavalMPCvalE,newPCvalMSEQHardwareStructureStagesFetchReadinstructionfrommemoryDecodeReadprogramregistersExecuteComputevalueoraddressMemoryReadorwritedataWriteBackWriteprogramregistersPCUpdateprogramcounterInstructionFlowReadinstructionataddressspecifiedbyPCProcessthroughstagesUpdateprogramcounterInstructionmemoryInstructionmemoryPCincrementPCincrementCCCCALUALUDatamemoryDatamemoryFetchDecodeExecuteMemoryWritebackicode,ifunrA,rBvalCRegisterfileRegisterfileABMERegisterfileRegisterfileABMEPCvalPsrcA,srcBdstA,dstBvalA,valBaluA,aluBBchvalEAddr,DatavalMPCvalE,valMnewPCDifferencebetweensemanticsandimplementationISAEverystagemayupdatesomestates,theseupdatesoccursequentiallySEQAllthestateupdateoperationsoccursimultaneouslyatclockrising(exceptCC)SEQHardwareKeyBlueboxes:predesignedhardwareblocksE.g.,memories,ALUGrayboxes:controllogicDescribeinHCLWhiteovals:labelsforsignalsThicklines:32-bitwordvaluesThinlines:4-8bitvaluesDottedlines:1-bitvaluesFetchLogicPredefinedBlocksPC:RegistercontainingPCInstructionmemory:Read6bytes(PCtoPC+5)Split:DivideinstructionbyteintoicodeandifunAlign:GetfieldsforrA,rB,andvalCFetchLogicControlLogicInstr.Valid:Isthisinstructionvalid?Needregids:Doesthisinstructionhavearegisterbytes?NeedvalC:Doesthisinstructionhaveaconstantword?FetchControlLogicbool

need_regids=

icodein{IRRMOVL,IOPL,IPUSHL,IPOPL, IIRMOVL,IRMMOVL,IMRMOVL};bool

instr_valid=icodein {INOP,IHALT,IRRMOVL,IIRMOVL,IRMMOVL,IMRMOVL, IOPL,IJXX,ICALL,IRET,IPUSHL,IPOPL};Decode&Write-BackLogicRegisterFileReadportsA,BWriteportsE,MAddressesareregisterIDsor8(noaccess)ControlLogicsrcA,srcB:readportaddressesdstA,dstB:writeportaddressesASourceOPl

rA,rBvalA

R[rA]DecodeReadoperandArmmovl

rA,D(rB)valA

R[rA]DecodeReadoperandApopl

rAvalA

R[%esp]DecodeReadstackpointerjXX

DestDecodeNooperandcall

DestvalA

R[%esp]DecodeReadstackpointerretDecodeNooperandint

srcA=[

icodein{IRRMOVL,IRMMOVL,IOPL,IPUSHL}:rA;

icodein{IPOPL,IRET}:RESP; 1:RNONE;#Don'tneedregister];EDestinationNoneR[%esp]

valEUpdatestackpointerNoneR[rB]

valEOPl

rA,rBWrite-backrmmovl

rA,D(rB)popl

rAjXX

Destcall

DestretWrite-backWrite-backWrite-backWrite-backWrite-backWritebackresultR[%esp]

valEUpdatestackpointerR[%esp]

valEUpdatestackpointerint

dstE=[

icodein{IRRMOVL,IIRMOVL,IOPL}:rB;

icodein{IPUSHL,IPOPL,ICALL,IRET}:RESP; 1:RNONE;#Don'tneedregister];ExecuteLogicUnitsALUImplements4requiredfunctionsGeneratesconditioncodevaluesCCRegisterwith3conditioncodebitsbcondComputesbranchflagControlLogicSetCC:Shouldconditioncoderegisterbeloaded?ALUA:InputAtoALUALUB:InputBtoALUALUfun:WhatfunctionshouldALUcompute?ALUAInputvalE

valB+–4DecrementstackpointerNooperationvalE

valB+4IncrementstackpointervalE

valB+valCComputeeffectiveaddressvalE

valBOPvalAPerformALUoperationOPl

rA,rBExecutermmovl

rA,D(rB)popl

rAjXX

Destcall

DestretExecuteExecuteExecuteExecuteExecutevalE

valB+4Incrementstackpointerint

aluA=[

icodein{IRRMOVL,IOPL}:valA;

icodein{IIRMOVL,IRMMOVL,IMRMOVL}:valC;

icodein{ICALL,IPUSHL}:-4;

icodein{IRET,IPOPL}:4; #Otherinstructionsdon'tneedALU];ALUOperationvalE

valB

+–4DecrementstackpointerNooperationvalE

valB

+4IncrementstackpointervalE

valB

+

valCComputeeffectiveaddressvalE

valB

OP

valAPerformALUoperationOPl

rA,rBExecutermmovl

rA,D(rB)popl

rAjXX

Destcall

DestretExecuteExecuteExecuteExecuteExecutevalE

valB

+4Incrementstackpointerint

alufun=[

icode==IOPL:ifun; 1:ALUADD;];ConditionSetBool

set_cc=icodein{IOPL};WewillnotdiscussthedetailofBcondThoughitisalsoacontrolunitMemoryLogicMemoryReadsorwritesmemorywordControlLogicMem.read:shouldwordberead?Mem.write:shouldwordbewritten?Mem.addr.:SelectaddressMem.data.:SelectdataMemoryAddressOPl

rA,rBMemoryrmmovl

rA,D(rB)popl

rAjXX

Destcall

Destret

NooperationM4[valE]

valAMemoryWritevaluetomemoryvalM

M4[valA]MemoryReadfromstackM4[valE]

valP

MemoryWritereturnvalueonstackvalM

M4[valA]MemoryReadreturnaddressMemory

Nooperationint

mem_addr=[

icodein{IRMMOVL,IPUSHL,ICALL,IMRMOVL}:valE;

icodein{IPOPL,IRET}:valA; #Otherinstructionsdon'tneedaddress];MemoryReadOPl

rA,rBMemoryrmmovl

rA,D(rB)popl

rAjXX

Destcall

Destret

NooperationM4[valE]

valAMemoryWritevaluetomemoryvalM

M4[valA]MemoryReadfromstackM4[valE]

valP

MemoryWritereturnvalueonstackvalM

M4[valA]MemoryReadreturnaddressMemory

Nooperationbool

mem_read=icodein{IMRMOVL,IPOPL,IRET};bool

mem_write

=icodein{IRMMOVL,IPUSHL,ICALL};PCUpdateLogicNewPCSelectnextvalueofPCPC

UpdateOPl

rA,rBrmmovl

rA,D(rB)popl

rAjXX

Destcall

DestretPC

valPPCupdateUpdatePCPC

valPPCupdateUpdatePCPC

valPPCupdateUpdatePCPCBch?valC:valPPCupdateUpdatePCPC

valCPCupdateSetPCtodestinationPC

valMPCupdateSetPCtoreturnaddressint

new_pc=[

icode==ICALL:valC;

icode==IJXX&&Bch:valC;

icode==IRET:valM; 1:valP;];SEQHardware

(Review)StagesoccurinsequenceOneoperationinprocessatatimeSEQ+HardwareStillsequentialimplementationReorderP