02集成电路工艺和版图设计参考

集成电路工艺和版图设计

概述

JianFang

ICDesignCenter,UESTC8/6/20241JianFang微电子制造工艺8/6/20242JianFangIC常用术语园片：硅片芯片(Chip,Die)：6

、8：硅（园）片直径：1

＝25.4mm6150mm;8200mm;12300mm;亚微米<1m的设计规范深亚微米<=0.5m的设计规范0.5m、0.35m－设计规范（最小特征尺寸）布线层数：金属（掺杂多晶硅）连线的层数。集成度：每个芯片上集成的晶体管数8/6/20243JianFangIC工艺常用术语净化级别：Class1,Class10,Class10,000每立方米空气中含灰尘的个数去离子水氧化扩散注入光刻…………….8/6/20244JianFang生产工厂简介PSI8/6/20245JianFangFabTwowascompletedJanuary2,2019andisa"StateoftheArt"facility.This2,200squarefootfacilitywasconstructedusingallthelatestmaterialsandtechnologies.Inthissetofcleanroomswechangetheair390timesperhour,

ifyoudothemathwithULPAfiltrationthisisaClassOnefacility.WehavehadittestedanditdoesmeetClassOneparameters(withoutanypeopleworkinginit).Sincewearenotmakingmicroprocessorshereandwedon'twanttowear"spacesuits",werunitasaclass10fab.EventhoughitconsistentlyrunswellbelowClassTen.8/6/20246JianFangHereintheFabTwo

Photolithographyareaweseeoneofour200mm.35micronI-LineSteppers.thissteppercanimageandalignboth6&8inchwafers.8/6/20247JianFangAnotherviewofoneoftheFabTwoPhotolithographyareas.8/6/20248JianFangHereweseeatechnicianloading300mmwafersintotheSemiTool.Thewafersareina13waferTefloncassetteco-designedbyProcessSpecialtiesandSemiToolin2019.Againthesearetheworld'sfirst300mmwetprocesscassettes(thatcanbespinrinsedried).8/6/20249JianFangAswelookinthiswindowweseetheWorld'sFirsttrue300mmproductionfurnace.Ourdevelopmentanddesignofthistoolbeganin1992,itwasinstalledinDecemberof2019andbecamefullyoperationalinJanuaryof2019.8/6/202410JianFangHerewecanseetheloadingof300mmwafersontothePaddle.8/6/202411JianFangProcessSpecialtieshasdevelopedtheworld'sfirstproduction300mmNitridesystem!Webeganprocessing300mmLPCVDSiliconNitrideinMayof2019.8/6/202412JianFang2,500additionalsquarefeetof"StateoftheArt"ClassOneCleanroomiscurrentlyprocessingwafers!Withincreased300mm&200mmprocessingcapabilitiesincludingmorePVDMetalization,300mmWetprocessing/Cleaningcapabilitiesandfullwafer300mm.35umPhotolithography,allinaClassOneenviroment.8/6/202413JianFangCurrentlyourPS300AandPS300Bdiffusiontoolsarecapableofrunningboth200mm&300mmwafers.Wecanevenprocessthetwosizesinthesamefurnaceloadwithoutsufferinganyuniformityproblems!(ThermalOxideOnly)8/6/202414JianFangAccuracyinmetrologyisneveranissueatProcessSpecialties.Weusethemostadvancedroboticlaserellipsometersandothercalibratedtoolsforprecisionthinfilm,resistivity,CDandstepheightmeasurement.IncludingournewNanometrics8300fullwafer300mmthinfilmmeasurementandmappingtool.WealsouseoutsidelaboratoriesandourexcellentworkingrelationshipswithourMetrologytoolcustomers,foradditionalcorrelationandcalibration.8/6/202415JianFangOneoftwoSEMLabslocatedinourfacility.InthisoneweareusingafieldemissiontoolforeverythingfromlookingatphotoresistprofilesandmeasuringCD'stodoublecheckingmetaldepositionthicknesses.Atthehelm,anotheroneofourprocessengineersyoumayhavespokenwithMarkHinkle.8/6/202416JianFangHerewearelookingattheIncomingmaterialdispositionracks

8/6/202417JianFangAboveyouarelookingatacoupleofviewsofthefacilitiesonthewestsideofFabOne.Hereyoucanseeoneofour18.5Meg/OhmDIwatersystemsandoneoffour

10,000CFMairsystemsfeedingthisfab(leftpicture),aswellasoneofourwaste

airscrubberunits(rightpicture).Bothareinsidethebuildingforeasiermaintenance,longerlifeandbettercontrol.8/6/202418JianFang集成电路（IntegratedCircuit,IC）：半导体IC，膜IC，混合IC半导体IC：指用半导体工艺把电路中的有源器件、无源元件及互联布线等以相互不可分离的状态制作在半导体上，最后封装在一个管壳内，构成一个完整的、具有特定功能的电路。半导体IC双极ICMOSICBiCMOSPMOSICCMOSICNMOSIC8/6/202419JianFangMOSIC及工艺MOSFET—MetalOxideSemiconductorFieldEffectTransistor.—金属氧化物半导体场效应晶体管Si金属氧化物（绝缘层、SiO2）半导体MOS(MIS)结构8/6/202420JianFangP－衬底n+n+漏源栅栅氧化层氧化层沟道GDSVTVGSIDVDS>0反型层沟道源（Source）S漏（Drain）D栅（Gate）G栅氧化层厚度：50埃－1000埃（5nm－100nm）VT－阈值电压电压控制N沟MOS（NMOS）

P型衬底，受主杂质；栅上加正电压，表面吸引电子，反型，电子通道；漏加正电压，电子从源区经N沟道到达漏区，器件开通。8/6/202421JianFangN－衬底p+p+漏源栅栅氧化层场氧化层沟道P沟MOS（PMOS）GDSVTVGSID+-VDS<0

N型衬底，施主杂质，电子导电；栅上加负电压，表面吸引空穴，反型，空穴通道；漏加负电压，空穴从源区经P沟道到达漏区，器件开通。8/6/202422JianFangCMOS

CMOS：ComplementarySymmetryMetalOxideSemiconductor

互补对称金属氧化物半导体－特点：低功耗VSSVDDVoViCMOS倒相器PMOSNMOSI/OI/OVDDVSSCCCMOS传输门8/6/202423JianFangN-SiP+P+n+n+P-阱DDVoVGVSSSSVDDCMOS倒相器截面图CMOS倒相器版图8/6/202424JianFangpwellactivepolyN+implantP+implantomicontactmetalANMOSExample8/6/202425JianFangpwellPwellActivePolyN+implantP+implantOmicontactMetal8/6/202426JianFangN－typeSiSiO2光刻胶光MASKPwell8/6/202427JianFangN－typeSiSiO2光刻胶光刻胶MASKPwell8/6/202428JianFangN－typeSiSiO2光刻胶光刻胶SiO28/6/202429JianFangN－typeSiSiO2SiO2Pwell8/6/202430JianFangpwellactivePwellActivePolyN+implantP+implantOmicontactMetal8/6/202431JianFangN－typeSiSiO2PwellSiO2光刻胶MASKactiveMASKActiveSi3N48/6/202432JianFangN－typeSiSiO2PwellSiO2光刻胶光刻胶MASKactiveMASKActiveSi3N48/6/202433JianFangN－typeSiSiO2PwellSiO2光刻胶光刻胶Si3N48/6/202434JianFangN－typeSiSiO2PwellSiO2场氧场氧场氧PwellSi3N48/6/202435JianFangN－typeSiSiO2Pwell场氧场氧场氧Pwell8/6/202436JianFangN－typeSiSiO2PwellSiO2场氧场氧场氧Pwellpoly8/6/202437JianFangactivepwellpolyPwellActivePolyN+implantP+implantOmicontactMetal8/6/202438JianFangN－typeSiSiO2PwellSiO2MASKpoly场氧场氧场氧Pwellpoly光刻胶8/6/202439JianFangN－typeSiSiO2PwellSiO2MASKpoly场氧场氧场氧Pwell光刻胶poly8/6/202440JianFangN－typeSiSiO2PwellSiO2场氧场氧场氧Pwellpoly8/6/202441JianFangN－typeSiSiO2PwellSiO2场氧场氧场氧Pwellpoly8/6/202442JianFangactivepwellpolyN+implantPwellActivePolyN+implantP+implantOmicontactMetal8/6/202443JianFangN－typeSiSiO2PwellSiO2MASKN+场氧场氧场氧Pwellpoly光刻胶8/6/202444JianFangN－typeSiSiO2PwellSiO2场氧场氧场氧Pwell光刻胶polyN+implantS/D8/6/202445JianFangactivepwellpolyP+implantPwellActivePolyN+implantP+implantOmicontactMetal8/6/202446JianFangN－typeSiSiO2PwellSiO2MASKN+场氧场氧场氧Pwellpoly光刻胶光S/D8/6/202447JianFangN－typeSiSiO2PwellSiO2场氧场氧场氧PwellS/Dpoly光刻胶P+implantP+接触8/6/202448JianFangN－typeSiSiO2PwellSiO2场氧场氧场氧PwellpolyS/DP+接触8/6/202449JianFangactivepwellpolyP+implantN+implantomicontactPwellActivePolyN+implantP+implantOmicontactMetal8/6/202450JianFangN－typeSiSiO2PwellSiO2MASKOmicontact场氧场氧场氧PwellpolyS/DP+接触8/6/202451JianFangactivepwellpolyN+implantomicontactmetalPwellActivePolyN+implantP+implantOmicontactMetal8/6/202452JianFangN－typeSiSiO2PwellSiO2MASKmetal场氧场氧场氧PwellpolyS/DP+接触metalmetalmetal8/6/202453JianFangpwellactivepolyN+implantP+implantomicontactmetal8/6/202454JianFang双极型IC及工艺NPN基极集电极发射极PNP基极集电极发射极CBEIBICIECBEIBICIENPN晶体管PNP晶体管8/6/202455JianFangVCEiCiBVCE(sat)iR双极型晶体管输出特性放大区饱和区电流放大能力；电流驱动；8/6/202456JianFang基极发射极N+N-PN+集电极基极发射极P+NNPEBBCCN＋CCBBEPP＋P＋PN＋N8/6/202457JianFang

BiCMOS:双极(Bipolar)与CMOS相容技术。

BiCMOS可以将双极器件与CMOS器件制作在同一芯片上，使之具有双极电路的高速度、高驱动能力、高模拟精度，又具有CMOS电路的低功耗、高集成度等特性。

BiCMOS工艺较之CMOS工艺和双极工艺都复杂，制作周期长，产品成品率比CMOS低，成本比CMOS高。高性能双极工艺与CMOS的VLSI工艺80％的工艺是相同的，在CMOS生产线上，只要改动或增添一部分工序，增添一部分设备，就可以制作BiCMOS芯片。BiCMOS8/6/202458JianFang版图设计（layout）及相关技术8/6/202459JianFangCelldevelopment(Analog/digital)

AnalogdesignSchematicentry(transistorsymbols)Analogsimulation(SPICEmodels)Layout(layerdefinitions)DesignRuleChecking,DRC(designrules)Extraction(extractionrulesandparameters)ElectricalRuleChecking,ERC(ERCrules)LayoutVersusSchematic,LVS(LVSrules)8/6/202460JianFangLayoutDrawinggeometricalshapes: Defineslayouthierarchy

DefineslayermasksRequiresdetailedknowledgeaboutCMOStechnologyRequiresdetailedknowledgeaboutdesignrules(hundredsofrules)RequiresdetailedknowledgeaboutcircuitdesignSlowandtediousOptimumperformancecanbeobtained8/6/202461JianFang图形层的定义N+implantmetalpwellactivePoly定义若干图层,每层对应一张掩膜版pwellactivepolyN+implantP+implantomicontactmetal8/6/202462JianFangLibALibBLibCCell1Cell2Cell3Tech

inst1inst2Inst3版图库的组织一个库对应一个特定的工艺针对该工艺的设计规则,和环境设定放在Tech文件中.

一个库可以包含若干不同层次的Cell.8/6/202463JianFang版图数据交换文件

GDSII格式

CIF格式

EDIF格式基本图形基本操作8/6/202464JianFangDRCDesignRuleCheckChecksgeometricalshapes: width,length,spacing,overlap,etc.

1.单层规则该规则包括各层的最小宽度a及同层间距b

层名称宽度a间距b层名称宽度a间距bn+保护环510p+注入区105有源区1010多晶硅布线88p+保护环510多晶硅栅68欧姆孔814布线铝条1010p阱11014电源、地线铝条2510n+注入区105p+墙58/6/202465JianFang

CMOS电路规则2.层间规则（包括各层间的间距、包围、迭搭的大小）8/6/202466JianFang说明标号尺寸（um）有源区包围欧姆孔a4金属（铝）包围欧姆孔b3多晶硅包围欧姆孔c4n+、p+注入区包围有源区d5n+、p+保护环~有源区e10n+、p+保护环宽度f5nmos、pmos多晶硅栅宽度g6多晶硅栅伸出有源区h12多晶硅栅与n+、p+保护环迭搭i2多晶硅栅~铝布线j1p阱包围p+保护环k2…………..8/6/202467JianFangDRC文件例子(片断) (drcmetal (width<1.00) ) (drcmetal (sep<0.80) ) (drcmetalomicont (enc<0.30) ) (drcpolyomicont (enc<0.40) )

8/6/202468JianFangEXTRACT用图层间的相对关系判定器件及相互连接关系.例如:Poly跨过Active,即同时出现Poly和Active表明有一个MOS器件.

Extractselectricalcircuit:

transistors,connections,capacitance,resistanceINOutVddGnd8/6/202469JianFangEXTRACT文件例子(片断)(extractDevicengate(poly"G")(nsd"S""D")(pwell1"B")"nmos4symbolanalogLib")(extractDevicepgate(poly"G")(psd"S""D")(sub"B")"pmos4symbolanalogLib")

pgateWidth=measureParameter(length(pgatecoincidentpoly)0.5) pgateLength=measureParameter(length(pgateinsidepoly)0.5) saveParameter(pgateWidth"W") saveParameter(pgateLength"L")

ngateWidth=measureParameter(length(ngatecoincidentpoly)0.5) ngateLength=measureParameter(length(ngateinsidepoly)0.5) saveParameter(ngateWidth"W") saveParameter(ngateLength"L")8/6/202470JianFangLVS10101010101040EXTLVSLayoutversusschematic

transistors:

parallelorserialCompareselectricalcircuits:

(schematicandextractedlayout)8/6/202471JianFangERCElectricalrulecheckCheckselectricalcircuit:unconnectedinputs

shortedoutputs

correctpowerandgroundconnection8/6/202472JianFangDigitaldesignBehavioralsimulation………………..Simulation/timingverificationwithestimatedback-annotationPlaceandroute(placeandrouterules)DesignRuleCheck,DRC(DRCrules)Loadingextraction(rulesandparameters)Simulation/timingverificationwithrealback-annotationDesignexport………..8/6/202473JianFangPlaceandRouteGeneratesfinalchipfromgatelevelnetlistGoals: Minimumchipsize

Maximumchipspeed.Placement:PlacingallgatestominimizedistancebetweenconnectedgatesFloorplanningtoolusingdesignhierarchySpecializedalgorithms(mincut,simulatedannealing,etc.)TimingdrivenManualinterventionVerycomputeintensiveHierarchybasedfloorplanningSimulatedannealingHightemperature:movegatesrandomlyLowtemperature:MovegateslocallyMincutKeepcuttingdesigninto