数字集成电路分析与设计-第七章答案

Assumethatallnodesstartat0V.Thefirstrowoutputswillbeat.Sincethesenodesarealsothegatenodesofthesecondrowoftransistors,theirsourcenodeswillbeat.Likewise,thelastrowoftransistorshavevoltagesof.However,thisvalueisbelow0Vsoweleavethemat0V.

(a)

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(d)

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(a)FirstcalculateVQ.

Sincethisisslightlybelow1.3V(voltageatwhichthePMOSturnson),weassumethatthePMOSisslightlyon.SincethePMOS’sVGSisquitelow(becauseQishigh)anditsVDSisquitehigh(becauseislow),thetransistorisverylikelyinsaturation.SimilarlyfortheNMOS,becauseitsVGSishighanditsVDSislow,it’slikelyinthelinearregion.Equatingthetwocurrents:

Forsimplicityweshallassumethatand.

Solvetoproduce:

WhentheCLKgoeslow,theintermediateoutputsuffersfromclockfeedthough.Tocalculatetheeffectsofclockfeedthrough,letusfirstcomputethecapacitancesinvolved.ThecapacitancefromtheclocksignaltoQis:

ThecapacitancefromtheQtogroundis:

Thecapacitivefeedthroughequationis:

Togetthenewvalueof,firstdeterminethedeterminetheregionsofoperationofthetransistorsintheinverterbycalculatingVS.Then,onceagain,usethecurrentequationstodetermine.

SincethenewvoltageofVQisstillgreaterthantheswitchingvoltage,thetransistorsareinthesameregions:

(b)Inthiscaseand.ClockfeedthroughhasnoeffectsincethetransmissiongateCLKsignalscanceleachotherout.

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Assumingthatoneofthetransistorsineachtransmissiongateisbeingdrivenbyamin-sizedinverter:

Inbothofthesecases,thelogicaleffortisthesameduetothefactthatthelongestpathfromoutputtogroundisthreetransistorslong.AssumethattheCLKarrivesaheadofthesignals.Then,

Wewilluse0.18umtechnologyandthenodenamesbelow:

Forthetwoinverterinputs:

Forthepassgateinputs:

Atnodex:

Atnodey:

AtnodeOut:

TheshortestpathisthroughtheoneoftheGNDinputnodestotheoutput:

Thelongestpathisthroughoneoftheinverterstotheoutput.

At:.

Whentheagoeshighthefirsttime,thevoltageatXwouldbecomputedusingthecharge-sharingformula:

Butbecausethemaximumallowablevoltageatnodexis0.734V,set

ThenrecomputedVF:

WhenPhigoesdown,andVXandVYremainsthesame.

ThenexttimethePhigoesup,alltheinternalnodesare0.

WhenPhigoesdown,andVXandVYremainsat0.

Static

Dynamic

Speed

Increaseintemperatureresultsinreducedspeedtoduetodecreaseinon-current.

Increaseintemperatureresultsinreducedspeedtoduetodecreaseinon-current.

Power

Increaseintemperatureresultsinincreasedpowerduetoincreaseinshort-circuitcurrentasaresultofreducedspeed.

Increaseintemperatureresultsinincreasedpowerduetoincreaseinshort-circuitcurrentasaresultofreducedspeed.

Leakage

Doesnotaffectoperationmuch,butincreasesstaticpower.

Increaseintemperatureresultsinincreaseofleakagecurrentandpossiblelossofvalue.

Theinputsettingsthatgiveyoutheworst-casechargesharingareanyofandbothof.Essentially,whatyouaredoingittryingtocreatethegreatestamountofparasiticcapacitanceswithoutcreatingapathtoGND.

Assumingthattransistorssharenodestoreducecapacitance.

TheactualvoltagewouldbelargerthanthissincetheinternalnodecannotriseaboveVDD-VT.

ThiscircuitfailsiftheworsecasevoltagefallsbelowtheswitchingvoltagewhichcanbecomputedtobeVS=0.92V.Therefore,thecircuitwilloperateproperly.

Bothofthesecircuitsactaslatches.WhenENison,thereisapathfromtheoutputtoeitherVDDorGND.Thefirstlatchisbetterthanthesecondbecausethesecondlatchsuffersfromchargesharing.WhenENisoff,thereisnopathfromtheoutputtoeitherofthesources,ifINisswitchingitispossibleforwhateverchargethatisheldonOUTtobesharedwith