数字电压表实验报告

数字电压表的综合设计一、设计题目：基于FPGA的数字电压表设计二、设计任务：1、具有0—2.5v的电压量程；2、通过LED灯显示2进制数字量；3、用FPGA设计制作成数字电压表的专用集成芯片，结合LED数码管构成一个能够实时显示的电压表。三、总体设计框图：1、总体框图22、分模块设计框图：LED数码管显示模块TL549A3、程序代码：查找表程序代码LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;entitychazhaobiaois port(V:instd_logic_vector(7downto0); q:outstd_logic_vector(11downto0) );endentitychazhaobiao;architecturebehavofchazhaobiaoissignalc30,c74,c117,d0,d1:std_logic;signalHB,LB:std_logic_vector(11downto0);begin --A/D值的高4位转换成3位BCD码HB<="001001000000"WHENV(7DOWNTO4)="1111"ELSE--2.40 "001000100100"WHENV(7DOWNTO4)="1110"ELSE --2.24 "001000001000"WHENV(7DOWNTO4)="1101"ELSE --2.08 "000110010010"WHENV(7DOWNTO4)="1100"ELSE --1.92 "000101110110"WHENV(7DOWNTO4)="1011"ELSE --1.76 "000101100000"WHENV(7DOWNTO4)="1010"ELSE --1.60 "000101000100"WHENV(7DOWNTO4)="1001"ELSE --1.44 "000100101000"WHENV(7DOWNTO4)="1000"ELSE --1.28 "000100010010"WHENV(7DOWNTO4)="0111"ELSE --1.12 "000010010110"WHENV(7DOWNTO4)="0110"ELSE--0.96 "000010000000"WHENV(7DOWNTO4)="0101"ELSE--0.80 "000001100100"WHENV(7DOWNTO4)="0100"ELSE --0.64 "000001001000"WHENV(7DOWNTO4)="0011"ELSE --0.48 "000000110010"WHENV(7DOWNTO4)="0010"ELSE --0.32 "000000010110"WHENV(7DOWNTO4)="0001"ELSE --0.16 "000000000000";--0.00 --A/D值低4位变为3位BCD码LB<="000000010101"WHENV(3DOWNTO0)="1111"ELSE--0.15"000000010100"WHENV(3DOWNTO0)="1110"ELSE --0.14 "000000010011"WHENV(3DOWNTO0)="1101"ELSE --0.13 "000000010010"WHENV(3DOWNTO0)="1100"ELSE --0.12 "000000010001"WHENV(3DOWNTO0)="1011"ELSE --0.11 "000000010000"WHENV(3DOWNTO0)="1010"ELSE --0.10 "000000001001"WHENV(3DOWNTO0)="1001"ELSE --0.09 "000000001000"WHENV(3DOWNTO0)="1000"ELSE --0.08 "000000000111"WHENV(3DOWNTO0)="0111"ELSE --0.07 "000000000110"WHENV(3DOWNTO0)="0110"ELSE --0.06 "000000000101"WHENV(3DOWNTO0)="0101"ELSE --0.05 "000000000100"WHENV(3DOWNTO0)="0100"ELSE --0.04 "000000000011"WHENV(3DOWNTO0)="0011"ELSE --0.03 "000000000010"WHENV(3DOWNTO0)="0010"ELSE --0.02 "000000000001"WHENV(3DOWNTO0)="0001"ELSE --0.01 "000000000000";--0.00 c30<='1'whenHB(3downto0)+LB(3downto0)>"01001"else '0'; d1<='1'whenHB(3downto0)>="1000"andLB(3downto0)>="1000"else '0'; c74<='1'whenHB(7downto4)+LB(7downto4)>"01001"else '0'; d0<='1'whenHB(7downto4)+LB(7downto4)="01001"else '0'; c117<='1'whenHB(11downto8)+LB(11downto8)>"01001"else '0'; q(3downto0)<= HB(3downto0)+LB(3downto0)+"0110"when c30='1'else HB(3downto0)+LB(3downto0)+"0110"when d1='1'else HB(3downto0)+LB(3downto0); q(7downto4)<= HB(7downto4)+LB(7downto4)+"0111"when c74='1'andc30='1'else HB(7downto4)+LB(7downto4)+"0110"when c74='1'andc30='0'else HB(7downto4)+LB(7downto4)+"0110"when c74='0'andc30='1'andd0='1'else HB(7downto4)+LB(7downto4)+"0001"when c74='0'and(c30='1'ord1='1')andd0='0'else HB(7downto4)+LB(7downto4); q(11downto8)<= HB(11downto8)+LB(11downto8)+"0111"when c117='1'andc74='1'else HB(11downto8)+LB(11downto8)+"0110"when c117='1'andc74='0'else HB(11downto8)+LB(11downto8)+"0001"when c117='0'andc74='1'else HB(11downto8)+LB(11downto8)+"0001"when c117='0'andc74='0'and(c30='1'ord1='1')andd0='1'else HB(11downto8)+LB(11downto8); end; 译码器程序代码LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;entityyimaisport(clk:instd_logic;d:instd_logic_vector(11downto0);seg:outstd_logic_vector(7downto0);sel:outstd_logic_vector(2downto0));endentityyima;architecturebehavofyimaissignalwei:std_logic_vector(2downto0);signalnum:std_logic_vector(3downto0);signala:std_logic_vector(2downto0);beginnum<=d(3downto0)whena="000"elsed(7downto4)whena="001"elsed(11downto8);seg(7)<='0'whenwei="011"else'1';wei<="110"whena="000"else"101"whena="001"else"011";sel<=wei;COM1:process(clk)beginifclk'eventandclk='1'thena<=a+1;ifa="010"thena<="000";endif;endif;endprocessCOM1;COM2:process(num)begincasenumiswhen"0000"=>seg(6downto0)<="1000000";--0when"0001"=>seg(6downto0)<="1111001";--1when"0010"=>seg(6downto0)<="0100100";--2when"0011"=>seg(6downto0)<="0110000";--3when"0100"=>seg(6downto0)<="0011001";--4when"0101"=>seg(6downto0)<="0010010";--5when"0110"=>seg(6downto0)<="0000010";--6when"0111"=>seg(6downto0)<="1111000";--7when"1000"=>seg(6downto0)<="0000000";--8when"1001"=>seg(6downto0)<="0010000";--9--when"1010"=>seg(6downto0)<="1110111";--when"1011"=>seg(6downto0)<="1111100";--when"1100"=>seg(6downto0)<="0111001";--when"1101"=>seg(6downto0)<="1011110";--when"1110"=>seg(6downto0)<="1111001";--when"1111"=>seg(6downto0)<="1110001";--whenothers=>seg(6downto0)<="0111111";whenothers=>seg(6downto0)<="1000000";endcase;endprocessCOM2;end;电压表顶层程序代码：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitydianyabiaoisPort(clk:instd_logic; --50m系统时钟 din:instd_logic; --（tlc549）串行数据输出端 clk_tlc549:outstd_logic;cs_tlc549:outstd_logic; --tlc549的片选信号输入端 shift:outstd_logic_vector(3downto0);--动态扫描时的位选信号 cs_led:outstd_logic_vector(1downto0);--发光二极管及数码管的片选信号输入端 dout_led:outstd_logic_vector(7downto0));--惧的发光器件的信号输出端enddianyabiao;architectureBehavioralofdianyabiaoistypestateis(st1,st2);signalcurrent_state:state;typestate1is(st0,st1,st2);signalcurrent_state1:state1;typestate2is(st0,st1,st2,st3,st4);signalcurrent_state2:state2;signalreg_datain:std_logic_vector(7downto0);signalreg_dout:std_logic_vector(15downto0);signaldout:std_logic_vector(4downto0);signalreg_din:integerrange0to80000;signalclk1m,clk1k,clk100:std_logic;begin--分频部分process(clk) --产生1MHz的频率variablecnt:integerrange0to50;beginifclk'eventandclk='1'thencnt:=cnt+1;ifcnt<50then ifcnt<25thenclk1m<='0'; elseclk1m<='1'; endif; elsecnt:=0; endif;endif;endprocess;process(clk1m) --产生1KHz的频率variablecnt:integerrange0to1000;beginifclk1m'eventandclk1m='1'thencnt:=cnt+1;ifcnt<1000then ifcnt<500thenclk1k<='0'; elseclk1k<='1'; endif; elsecnt:=0;endif;endif;endprocess;process(clk1k) --产生100Hz的频率variablecnt:integerrange0to10;beginifclk1k'eventandclk1k='1'thencnt:=cnt+1;ifcnt<10then ifcnt<5thenclk100<='0'; elseclk100<='1'; endif;elsecnt:=0; endif;endif;endprocess;--tlc549的控制部分process(clk1k)variablecnt:integerrange0to7;variabledatain:std_logic_vector(7downto0);beginifclk1k'eventandclk1k='1'thencasecurrent_stateiswhenst1=> --将数据进行串并转换 cs_tlc549<='0'; datain:=datain(6downto0)&din; --将读取的数据向高位移位 clk_tlc549<='1'; current_state<=st2;whenst2=> cs_tlc549<='0'; clk_tlc549<='0'; current_state<=st1; ifcnt<7thencnt:=cnt+1; --读取8位数据 elsecnt:=0; reg_din<=conv_integer(datain)*195;--每单位数字量乘以系数＝当前电压值； reg_datain<=not(datain); endif;whenothers=> current_state<=st1;endcase;endif;endprocess;--十进制－BCD码转换；process(clk100) variablereg:integerrange0to80000;variabled1,d2,d3,d4:std_logic_vector(3downto0);beginifclk100'eventandclk100='1'thencasecurrent_state1is whenst0=> reg:=reg_din; d1:="0000";d2:="0000";d3:="0000";d4:="0000"; current_state1<=st1;whenst1=> ifreg>9999thenreg:=reg-10000;d1:=d1+1; elsifreg>999thenreg:=reg-1000;d2:=d2+1; elsifreg>99thenreg:=reg-100;d3:=d3+1; elsifreg>9thenreg:=reg-10;d4:=d4+1; elsecurrent_state1<=st2; endif;whenst2=> reg_dout<=d1&d2&d3&d4; current_state1<=st0;whenothers=> current_state1<=st0;endcase;endif;endprocess;--动态扫描控制；process(clk1k)beginifclk1k'eventandclk1k='1'thencasecurrent_state2iswhenst0=> --在发光二极管上显示模数转换后的数字量cs_led<="01";--熄灭数码管 shift<="1111"; dout<="11111";current_state2<=st1;whenst1=> --在数码管的最高位显示数据 cs_led<="10"; --熄灭发光二极管 shift<="0111"; --最高位数码管显示 dout<='0'®_dout(15downto12); --小数点显示，并且将最高位的数据送给译码器 current_state2<=st2;whenst2=> --在数码管的次高位显示数据 cs_led<="10"; --熄灭发光二极管 shift<="1011"; --次高位数码管显示 dout<='1'®_dout(11downto8); --小数点不显示，将次高位的数据送给译码器 current_state2<=st3; whenst3=> --在数码管的次低位显示数据 cs_led<="10"; --熄灭发光二极管 shift<="1101"; --次低位数码管显示 dout<='1'®_dout(7downto4); --小数点不显示，将次低位的数据送给译码器 current_state2<=st4;whenst4=> --在数码管的最低位显示数据 cs_led<="10"; --熄灭发光二极管 shift<="1110"; --最低位数码管显示 dout<='1'®_dout(3downto0); --小数点不显示，将最低位的数据送给译码器 current_state2<=st0;