备注使用dc2007lab工程在dc2009软件上运行通记录h

基本概念链接库(linklibrary):希望自己的设计去链接的库有设置约束才有时序报surootchmod-R777Task3.读取设计文symbol库名是.../ref/db/sc.sdbscrips则包括了约束文件如下如下write-hier-fddc-out由于目前设计还没有编译,所以在原理图中看到的是GTECH（GTECH库是Synopsys公司提供的通用的、独立于工艺的元件库。Synopsys公司提供的综合工具DC把综合分为三个步骤进 库元件映射到某一特定的半导体工艺库上，此时的电路网表包含了相关的工艺参数repeatthisstepforFSM,andrepeatthisstepforFSM,andsourceTask7.编译或者映射为Vendor- design_vision>Information:EvaluatingDesignWarelibraryutilization.(UISN-|DesignWareBuildingBlock||Available|BasicDWBuilding|LicensedDWBuilding|C-2009.06-DWBB_0906*||||Information:Thereare19potentialproblemsinyourdesign.Pleaserun'check_design'formoreinformation.(LINT-99)BeginningPass1Processing'COUNT'Processing'FSM'Processing'TOP'UpdatingtimingInformation:Updatingdesigninformation...(UID-Optimization 是根据设计者设定的时延、面积、线负载模型等综合约束条件对电路网表进一步）编译属于映射这BeginningImplementationProcessingBeginningMapping(MediumMappingOptimization(Phase1)MappingOptimization(Phase2)MappingOptimization(Phase3)WORSTNEGTOTALBeginningImplementationProcessingBeginningMapping(MediumMappingOptimization(Phase1)MappingOptimization(Phase2)MappingOptimization(Phase3)WORSTNEGTOTALBeginningDelayOptimizationWORSTNEGTOTAL RULEBeginningArea-RecoveryWORSTNEGTOTAL RULELoadingdbfileOptimization1Currentdesignis'TOP'.Warning:Indesign'DECODE',port'Crnt_Instrn[26]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[24]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[15]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[14]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[13]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[12]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[11]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[10]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[9]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[8]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[7]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[6]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[5]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[4]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[3]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[2]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[1]'isnotconnectedtoanynets.(LINT-28)Warning:Indesign'DECODE',port'Crnt_Instrn[0]'isnotconnectedtoanynets.(LINT-28)youwillseevarioustablesforthe differentoptimizationphasesofcompile径.(即实际延迟-期望延迟)TOTALNEGSLACK是violatingpathslacks的总数。当软件优化达到一个节点时，或Task8.生成报告与时序分析回到TOP的Symbolreport_constraint-Report:constraintDesign:TOPVersion:C-2009.06:TueJun1704:26:35min_delay/hold('Clk'PathPath0.000.000.000.000.000.000.000.00report_constraint-Report:constraintDesign:TOPVersion:C-2009.06:TueJun1704:26:35min_delay/hold('Clk'PathPath0.000.000.000.000.000.000.000.000.000.000.000.000.000.000.000.000.000.000.001(可以产生report_timing报告WorstTimingViolation:Slack(VIOLATED)Report:timing-path-delayDesign:TOPVersion:C-:TueJun1704:25:42WireLoadModelMode:topLibrary:Startpoint:Neg_Flag(可以产生report_timing报告WorstTimingViolation:Slack(VIOLATED)Report:timing-path-delayDesign:TOPVersion:C-:TueJun1704:25:42WireLoadModelMode:topLibrary:Startpoint:Neg_Flag(inputportclockedbyClk)Endpoint:I_COUNT/PCint_reg[0](risingedge-triggeredflip-flopclockedbyClk)PathGroup:ClkPathType:WireLoadclockClk(riseinputexternaldelayNeg_Flag(in)I_DECODE/Neg_Flag(DECODE)I_DECODE/I_14/Z(GTECH_NOT)I_DECODE/C163/Z(GTECH_AND2)I_DECODE/C167/Z(GTECH_OR2)I_DECODE/I_12/Z(GTECH_NOT)I_DECODE/Incrmnt_PC(DECODE)I_COUNT/Incrmnt_PC(COUNT)I_COUNT/I_1/Z(GTECH_NOT)I_COUNT/B_3/Z(GTECH_BUF)I_COUNT/C98/Z_0dataarrivaltimeff11.21clockClk(riseclockuncertaintylibrarysetuptimedatarequireddataarrivaltimeslack1Report:areaDesign:TOP:TueJun171Report:areaDesign:TOP:TueJun1704:24:29Library(s)gtech(File:Numberofports:Numberofnets:Numberofcells:33Combinationalarea:NetInterconnectarea:Totalarea:SchematicViewof蓝色,否则工具栏里的CriticalPath选项会是灰色)关键路径(也就是有最大violation的路径),将会高亮.Pushinandoutofthehierarchytofollowthiscritical取消高亮可以选择Highlight=>clearAll(CTRL-然后选择三个按钮中的中间一个,Createndpointslack包含的路径的详细细节(TimingSlackandEndpoint),如下图所示:AddPathSchematicofSelectedLogic按钮,如下这会增加连接至电路末尾节点（endpoint这会增加连接至电路末尾节点（endpoint）的路径.“AddFamin/FanouttoPathSchematic”(也就是软Task9.保存优化后的设然后保存该设计,针对未映射(unmapped)和映射[mapped(compiled)]的设计而言,NativeDCXG模式下的文件保存格式是以.ddc为后缀.mapped文件夹内,输入TOP.ddc保存现在已经把门级网表[(gate-levelnetlist)以ddc格式保存在mapped文件夹下了.下一步,选择DC界面左下方的History标签,SaveContentAstcltcl文件保存在scripts文件夹下Task10.移除设计,退出fr代表remove_designcpcommand.longlab2.logdesign_vision-fdesign_vision-fscripts/run_history.tclTask12.为下一个实验预先建chmodu+x文件接下来我们会接触到更加强大的名compile_ultra,这个命令首先对技术库文件(technologyTask1.确定目标库的时间单输入redirectfilelib.rpt(report_liblibrary_NAME>)失败在scripts文件夹中建立新文件lab4.conmancreate_clockdcprocheckscripts/lab4.con(找dcprocheckscripts/lab4.con(找不到这条命令)dcprocheckprefersthecommandread_filefverilogsourcescripts/lab4.conreport_clock-skewwrite_script-outscripts/lab4.wscrdiff命令可以用来检查你写的script文件和隐藏文件夹.solution中提供的文件是否Error:unknowncommand'tkdiff'(CMD-005)design_vision>diffscripts/lab4.wscr.solutions/lab4.wscrError:unknowncommand'diff'(CMD-005)需要注意,targetlibraryfilename指的sc_max.db,targetlibraryname指的是cb13fs120_tsmc_max,DC常用单位是1ns,对于任何约束文件推荐的第一条处理命令是实验五.设计划分与综合结mapped的文件夹中导ddc文件,然后createndpointslackhistogram生成时(Red=NegtiveMaxDelay:LargestViolation(Slack)-Totalcellarea:429.023048然后点击该路径再次使其高亮后，如双击该模块进入，双击该模块进入，可以知道该路径连接到了底层模块内部的哪里（图中黄色线），如下：设法改善约束，然后输入 来清除之前的一切操作，为下一实验做准备Task2.重新划分未映射的设读取unmapped文件夹中TOP.ddc同时选I_DECODEI_COUNTget该命令应{I_DECODE把这两个模块组合在一起并给予新的设计名称：NEW给予新的元件名称：输入group-designNEW-cellI_NEW观看新建立的元件I_NEW（以上命令是把I_FSM、I_DECODE三个模块中的后两个模块组合成一个新的模块I_NEW，也就是所设计划分也可以通过设计划分也可以通过以下命令观看设计层report_hierarchy-noleafdesign_vision>report_hierarchy-noleafReport:Design:TOPVersion:C-:TueJun1719:11:34Information:Thisdesigncontainsunmappedlogic.(RPT-11不再是模块化，但是又指定了level，因此我的理解是把底层小模块打散，高层模块保留ungroup-start_level2I_NEW输design_vision>Information:EvaluatingDesignWarelibraryutilization.(UISN-|||DesignWareBuildingBlockLibraryAvailable||BasicDWBuilding|C-2009.06-|*||LicensedDWBuilding|C-2009.06-|*|Information:Thereare1potentialproblemsinyourdesign.Please'check_design'formoreinformation.(LINT-BeginningPass1'check_design'formoreinformation.(LINT-BeginningPass1Processing'FSM'ProcessingUpdatingtimingInformation:Updatingdesigninformation...(UID-BeginningImplementationProcessing(MediumBeginningMappingMappingOptimization(Phase1)MappingOptimization(Phase2)MappingOptimization(PhaseMappingOptimization(PhaseWORSTNEGTOTALRULE---------------------------------------------------------------------BeginningDelayOptimizationWORSTNEGTOTALRULE---------------------------------------------------------------------BeginningArea-RecoveryWORSTNEGTOTALBeginningArea-RecoveryWORSTNEGTOTALRULE---------------------------------------------------------------------LoadingdbfileOptimization1Currentdesignis'TOP'.design_vision>rcInformation:Updatingdesigninformation...(UID-Report:Design:TOPReport:Design:TOPVersion:C-:TueJun1719:17:21Thisdesignhasnoviolated6.环境读取rtl文件夹下的my_design.vreport_port-v好模型的工作条件（这个我理解就是和ic5141类似的器件工作时的section）。实验9.更多的约束lab9BIsolateanyoutputportthatfansoutinternallytothedesign,fromexternalloads（翻译不好）Analyzing:LibraryanalysisInformation:EvaluatingDesignWarelibraryutilization.(UISN-|||DesignWareBuildingBlockLibraryAvailable||||DesignWareBuildingBlockLibraryAvailable||C-2009.06-DWBB_0906*|BasicDWBuilding||C-2009.06-DWBB_0906*|LicensedDWBuilding|SVFfilemustInformation:Sequentialoutputinversionisenabled.usedforformalverification.(OPT-1208)Information:Thereare2potentialproblemsinyourdesign.Please'check_design'formoreinformation.(LINT-Loadedalibfile'../alib-BuildingmodelLoadedalibfile'../alib-BuildingmodelInformation:UngroupinghierarchyU1_ARITHbeforePass1(OPT-Information:UngroupinghierarchyU_COMBObeforePass1(OPT-Information:UngroupinghierarchyU_COMBO/U2_ARITHbeforePass1Information:Ungrouping3of4hierarchiesbeforePass1(OPT-BeginningPass1ProcessingImplementSyntheticforUpdatingtimingInformation:Updatingdesigninformation...(UID-BeginningMapping(UltraInformation:Updatingdesigninformation...(UID-BeginningMapping(UltraHighInformation:Addedkeylist'DesignWare'todesign'MY_DESIGN'.Information:Indesign'MY_DESIGN',theregister'R3_reg[0]'isbecauseitismergedto'R1_reg[0]'.(OPT-Re-synthesisOptimization(PhaseRe-synthesisOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimizationGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseBeginningDelayOptimizationWORSTNEGTOTALRULEBeginningArea-RecoveryBeginningArea-Recovery(max_areaWORSTNEGTOTALRULEGlobalOptimization(PhaseGlobalWORSTNEGTOTALRULEGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimizationGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseGlobalOptimization(PhaseLoadingdbfileOptimization1Currentdesignisreport_constraintall_violoators(没有找到Report:areaDesign:report_constraintall_violoators(没有找到Report:areaDesign:MY_DESIGNVersion:C-2009.06:TueJun1722:52:43Library(s)Numberofports:Numberofnets:Numberofcells:NumberofCombinationalNoncombinationalNetInterconnectTotalcellTotal1本实tcl文件里没有约束指标本实验会看到输出端口和内部时序路径相连接，我们需要把输出端口从内部时许路径隔离。从lab9启动，读取mapd中的ddcsourcesource然后再改30f相对于内部的电路网络而言，I/O端口有更大的WLM，也有更大的扇出，输出端口时延远是什么导致了输入sel的延时，Incr这个表示带有过渡时间（翻转期间所需时间）输入信号到达翻转点（0=>1或者1=>）所需要的额外的时间。第一个逻辑门的输入引脚是单独报告的，因为它的延时不是由于电路网络所导致的。你怎么知道O路径，从输入到输出是2.45ns的延时呢？“daterequiredtime”(3.45to3.85ns)-datearrivaltimeattheinput通过以下命令可以看到没有冲突report_constraints-以下命令可以让输出端口独立于内部路径，该命令可以让输出端口与内部路径相隔离，让部延时独立于外部输出set_isolate_ports-typeinverter\10.多相时钟与时序例基本概念这时候就可以设置multicycle，这样综合的时候就不用把速度做的那么快design_vision>linkLinkingdesignLinkingdesignUsingthefollowingdesignsand*(7dw_foundation.sldb(library)cdvvv任务任务小节：不同路径需要分Task2.分别约束create_clock-namevclk-periodreport_timing-grouppathgroupvclkvrt-to!!!!-delayvvreport_constraint-read_fileread_file-formatverilogInformation:Updatingdesigninformation...(UID-Design:STOTOVersion:C-2009.06:WedJun1805:08:14GroupName Design:STOTOVersion:C-2009.06:WedJun1805:08:14GroupName PathGroup-compile_auto_ungroup_area_num_cells="30"compile_auto_ungroup_override_wlm="false"输入get_attribute[get_designs"PIPELINEINPUT"]Warning:Attribute'ungroup'doesnotexistondesign'PIPELINE'.(UID-101)Warning:Attribute'ungroup'doesnotexistondesign'INPUT'.(UID-101)Report:timing_requirementsDesign:STOTOVersion:C-2009.06:WedJun1805:12:33get_designs{STOTOMIDDLEPIPELINEDONT_PIPELINEGLUEARITHRANDOMINPUTOUTPUTreport_hierarchy-Report:Design:STOTO:WedJun1805:16:31r-licensedrredirect-tee-filerc_compile_ultra.rptReport:Design:STOTOVersion:C-2009.06:WedJun1805:17:31max_delay/setup('clk'PathPath2.322.312.312.312.332.312.292.302.252.20Report:Design:STOTOVersion:C-2009.06:WedJun1805:17:31max_delay/setup('clk'PathPath2.322.312.312.312.332.312.292.30092.092.092.092.092.092.092.092.072.052.042.042.041.991.991.991.87-0.071.98-0.051.87-0.071.98-0.05-24.70一系列问题的解design_vision>get_attribute[get_designs"PIPELINEINPUT"]Warning:Attribute'ungroup'doesnotexistondesign'PIPELINE'.(UID-101)Warning:Attribute'ungroup'doesnotexistondesign'INPUT'.这个命令用来验证PIPELINEINPUT是否具备ungroup属-对于有高低层层次逻辑关系的电路，不适合对这些逻辑层次进行设计划分。时序中，一般IO约束是保守的，目的是满足寄存器和寄存器之间的时序关系，最大延时max-delay一般不是最关键的。exception可能会掩盖寄存器之间的时序约束冲突。get_cell-hier{I_MIDDLE/I_PIPELINE/z_reg[9]I_MIDDLE/I_PIPELINE/z_reg[7]I_MIDDLE/I_PIPELINE/z_reg[8]I_MIDDLE/I_PIPELINE/z_reg[0]I_MIDDLE/I_PIPELINE/z_reg[5]I_MIDDLE/I_PIPELINE/z_re