数字电路实验报告

实验一、半加器与全加器的电路图实现半加器1、半加器的电路图——见图1图1——半加器的电路图2、半加器仿真波形图——见图2图2——半加器仿真波形图3、仿真图简析：如图2，为半加器仿真波形图。对应a,b输入波形，得到的c为进位，s为和。如a=1，b＝0，c=0,s=1.4、半加器的VHDL语言为：libraryieee;useieee.std_logic_1164.all;entitytx23p31isport(a,b:instd_logic;co,so:outstd_logic);endentitytx23p31;architectureaoftx23p31isbeginso<=axorb;co<=aandb;end;全加器1、全加器的电路图——见图3图3——全加器的电路图2、全加器的VHDL语言libraryieee;useieee.std_logic_1164.all;entitytx23p3isport(ain,bin,cin:instd_logic;cout,sum:outstd_logic);endentitytx23p3;architectureaoftx23p3iscomponenttx23p31port(a,b:instd_logic;co,so:outstd_logic);endcomponent;signald,e,f:std_logic;beginu1:tx23p31portmap(a=>ain,b=>bin,co=>d,so=>e);u2:tx23p31portmap(a=>e,b=>cin,co=>f,so=>sum);cout<=dorf;end;3、全加器的RTLviewer：见图4图4——全加器的RTLviewer

实验二、函数发生器1、电路图——见图5图5——函数发生器的实验电路图2、函数发生器的仿真波形图——见图6图6——函数发生器的仿真波形图3、波形图仿真分析：如上图，当a,b,c的取值为0，4，6，7时，f＝1；其他时刻，f＝0。如第一列波形，a=0,b=0,c=0,此时f=1.

实验三、四选一数据选择器libraryieee;useieee.std_logic_1164.all;entitytx23w1is port(a:instd_logic_vector(1downto0); d:instd_logic_vector(3downto0); y:outstd_logic);endtx23w1;architecturemux4oftx23w1isbegin process(a,d) begin caseais when"00"=>y<=d(0); when"01"=>y<=d(1); when"10"=>y<=d(2); when"11"=>y<=d(3); whenothers=>y<='0'; endcase; endprocess;endmux4;图7——四选一数据选择器波形图

实验四、裁判器libraryieee;useieee.std_logic_1164.all;entitytx23w2is port(a:instd_logic_vector(2downto0); y:outstd_logic_vector(1downto0));endtx23w2;architecturemux8oftx23w2isbegin process(a) begin caseais when"000"=>y<="00"; when"001"=>y<="00"; when"010"=>y<="00"; when"011"=>y<="10"; when"100"=>y<="10"; when"101"=>y<="11"; when"110"=>y<="11"; when"111"=>y<="11"; whenothers=>y<="00"; endcase; endprocess;endmux8;图8——裁判表决器实验五、50M分频器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitytx23w3isport(clk:instd_logic;clear:instd_logic;clk_out:outstd_logic);endtx23w3;architectureaoftx23w3issignaltmp:integerrange0to50000000;beginp1:process(clear,clk)beginifclear='0'thentmp<=0;elsifclk'eventandclk='1'theniftmp=49999999thentmp<=0;elsetmp<=tmp+1;endif;endif;endprocessp1;p2:process(clk,tmp)beginif(clk'eventandclk='1')theniftmp>=25000000thenclk_out<='1';elseclk_out<='0';endif;endif;endprocessp2;enda;

实验六、七段荧光屏数码显示学号libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitiytx23h1isport( clk:instd_logic; seg:outstd_logic_vector(6downto0); cat:outstd_logic_vector(5downto0));endtx23h1;architectureaoftx23h1is signaltmp:integerrange0to5; signalclk_tmp:integerrange0to100000; signalclk_out:std_logic; signalmove:begin p1:process(clk)begin if(clk'eventandclk='1')then ifclk_tmp=49999then clk_tmp<=0; clk_out<=notclk_out; elseclk_tmp<=clk_tmp+1; endif; endif; endprocessp1;//进程一：分频系数为100000的分频器 p2:process(clk_out) begin if(clk_out'eventandclk_out='1')then iftmp=5thentmp<=0;elsetmp<=tmp+1; endif; endif;endprocessp2; //进程二：模制为六的计数器 p3:process(tmp) begin casetmpis when0=>seg<="0110000"; when1=>seg<="1101101"; when2=>seg<="1111110"; when3=>seg<="1111111"; when4=>seg<="1101101"; when5=>seg<="1111001"; endcase; endprocessp3;//进程三：不同计数器的计数值时的显示数字，从0~5为：120823p4:process(tmp)begin casetmpiswhen0=>cat<="011111";when1=>cat<="101111";when2=>cat<="110111";when3=>cat<="111011";when4=>cat<="111101";when5=>cat<="111110";//进程四：选择输出的荧光屏数码管endcase;endprocessp4;enda;

实验七、实现自己学号滚动的七段荧光屏数码显示libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitytx23h2is port(clk:instd_logic; seg:outstd_logic_vector(6downto0); cat:outstd_logic_vector(5downto0));endtx23h2;architectureaoftx23h2is signalcnt1:integerrange0to49999; signalcnt2:integerrange0to499; signalclk_tmp1:std_logic; signalclk_tmp2:std_logic; signalq_tmp1:integerrange0to5; signalq_tmp2:integerrange0to5;begin p1:process(clk) begin if(clk'eventandclk='1')then ifcnt1=49999then cnt1<=0; clk_tmp1<=notclk_tmp1; else cnt1<=cnt1+1; endif; endif; endprocessp1;//分频系数为100000的分频器 p2:process(clk_tmp1)beginif(clk_tmp1'eventandclk_tmp1='1')then ifcnt2=499then cnt2<=0; clk_tmp2<=notclk_tmp2; else cnt2<=cnt2+1; endif; endif; endprocessp2;//分频系数为1000的分频器，使最后的滚动时间变为2秒 p3:process(clk_tmp1)beginif(clk_tmp1'eventandclk_tmp1='1')thenifq_tmp1=5thenq_tmp1<=0;elseq_tmp1<=q_tmp1+1;endif;endif;endprocessp3;//计数器，模制为6，第一个时钟的时钟沿有效p4:process(clk_tmp2)beginif(clk_tmp2'eventandclk_tmp2='1')thenifq_tmp2=5thenq_tmp2<=0;elseq_tmp2<=q_tmp2+1;endif;endif;endprocessp4;//计数器，模制为6，第二个时钟的时钟沿有效p5:process(q_tmp1)begincaseq_tmp1iswhen0=>seg<="0110000";//通过计数器1的值选择要输出的信息，为120823when1=>seg<="1101101";when2=>seg<="1111110";when3=>seg<="1111111";when4=>seg<="1101101";when5=>seg<="1111001";whenothers=>seg<="1111111";endcase;endprocessp5;p6:process(q_tmp1,q_tmp2)begincase(q_tmp1+q_tmp2)rem6is//q_tmp1+q_tmp2为两个计数器的计数值之和，模when0=>cat<="011111";//六之后的数值进行循环，用余数选择荧光数码管when1=>cat<="101111";//实现学号的滚动输出，这一步是本电路的核心；when2=>cat<="110111";when3=>cat<="111011";when4=>cat<="111101";when5=>cat<="111110";whenothers=>cat<="000000";endcase;endprocessp6;enda;（注：为了是波形显示有序清晰，重新修改了代码、重新设置了分频器的系数等参数，将显示在数码管上的数据改成了012345）图9——七段荧光屏数码显示图10——七段荧光屏数码滚动显示波形图

实验七、发光二极管走马灯电路设计与实现——状态机的设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYtx23h3IS PORT( clk:INSTD_LOGIC; clear:INSTD_LOGIC; swich:INSTD_LOGIC; q_out:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDtx23h3;ARCHITECTUREaOFtx23h3IS SIGNALtmp:INTEGERRANGE0TO7;//定义结构体内部信号为从0-7的整型SIGNALe:STD_LOGIC; COMPONENTdiv50m//加入50分频 PORT(clk_in:INSTD_LOGIC; clk_out:OUTSTD_LOGIC); ENDCOMPONENT;BEGINu1:div50mPORTMAP(clk_in=>clk,clk_out=>e); p1:PROCESS(e) BEGIN IFe'eventANDe='1'THEN//检测到时钟的上升沿 IFtmp=7THEN tmp<=0; ELSE tmp<=tmp+1;//信号依次改变 ENDIF; ENDIF;ENDPROCESSp1;//进