论出口对中国经济增长的贡献及TMS320C5402外文文献及译文

PAGE论出口对中国经济增长的贡献内容提要：本文使用一种叫做自回归分布滞后—非约束误差纠正模型(ARDL-UECM)的方法来检验Thirlwall定律在中国的适用性，并测度长期中出口对经济增长的贡献程度。结果表明，长期中，Thirlwall定律在中国成立。1980—2010年间，出口每增长10%，将推动GDP增长约1.8%。这个值大于林毅夫和李XX2003年估计的1%，这表明他们的估计方法存在的缺陷可能确实对结果产生了较大的影响。出口对经济增长的影响如此之大，所以我国有必要保持外贸的稳定增长。关键词：出口，中国经济增长，Thirlwall定律，ARDLUECM方法作者简介：王俊杰，华中科技大学经济学院一、引言1978—2010年，我国对外贸易取得了飞速发展，进出口总额从1978年的206.4亿美元增加到2010年的29727.6亿美元，其中进口从108.9亿美元增加到13948.3亿美元，出口从97.5亿美元增加到15779.3亿美元。折算成增长率，进口年均增长16.37%，出口年均增长17.23%，而同期中国GDP年均增长9.9%。出口对于经济增长的巨大作用得到了许多文献的证实(Thirlwall，1979，1983，2003；Feder，1983；徐长生和庄佳强，2008；Jeon，2008)。林毅夫和李XX(2003)还实证研究了出口对中国经济的贡献程度，结果表明，20世纪90年代，外贸出口每增长10%，基本上能够推动GDP增长1%。但是林毅夫和李XX的模型设定和估计方法存在问题。由于他们的基本模型受到多重共线性的困扰，他们不得不去掉多个变量，这可能对结果产生了重大影响。本文根据Thirlwall的理论，并使用一种叫做自回归分布滞后—非约束误差纠正模型(ARDL-UECM)的方法来测度出口对经济增长的贡献程度。这种方法在测度变量之间的长期关系时非常有效，且它的一个突出的优点是它允许解释变量都是I(0)或者I(1)，或者是二者的混合，只要被解释变量是I(1)。此外，它对于小样本而言，也相当有效。二、文献综述Kaldor(1957)认为，出口是需求的一部分，出口需求的增加倾向于导致更好的供给条件，如更多的产出将导致更高的劳动生产率，而这将反过来导致更多的出口需求，因为更高的生产率意味着更多的供给和更好的贸易条件。Thirlwall(1979)沿着Kaldor的思路，提出国际收支平衡约束下的经济增长。在开放经济条件下，一国经济要想持续增长，伴随着经济增长的进口需求增长必须由出口增长带来的外汇收入来支持。因此，一国经济增长受到国际收支平衡的约束，长期中，一国经济增长率与出口增长率正相关，且一国经济要想持续增长，出口的增长速度必须快于进口的增长速度。在Thirlwall的理论体系中，模型来自最基本的收支平衡方程：PX+EF=EPfM(1)其中，P是以本国货币表示的价格水平，X是对本国产品的出口需求，E是用一单位外国货币的本币价格表示的名义汇率，F是以外币表示的净资本流入，Pf是以外币表示的外国价格水平，M是本国的进口需求数量。方程中，F＞0表示资本流入，F＜0则意味着资本流出。最后定义出口收入占从国外取得的总收入的比例如下：θ=PX/(PX+EF)(2)出口需求函数用常用形式：X=(P/EPf)ηZε(3)其中，Z表示贸易伙伴的实际收入，η和ε表示外国对本国出口需求的价格弹性和收入弹性。因此，如根据标准需求理论，η＜0，ε＞0。类似地，进口需求函数表示如下：M=(EPf/P)ψYπ(4)其中，Y是国内实际收入，ψ和π分别表示国内对进口产品需求的价格弹性和收入弹性，ψ＜0，π＞0。对(1)、(3)、(4)式两边取对数并微分，并利用方程(2)得：θ(p+x)+(1-θ)(e+f)=e+pf+m(5)x=η(p-e-pf)+εz(6)m=ψ(pf+e-p)+πy(7)其中小写字母表示以上所定义变量的增长率。将(6)、(7)式代入方程(5)，并解出y，可以得到以下等式：(8)上式中，y加有下标b表示本国收入的增长率受到国际收支平衡的约束。上式中，等式右边第一项表示外生的国外收入变化通过出口需求的收入弹性对本国产出增长的影响；第二项表示贸易条件变化产生的影响；第三项则表示资本流入变化对国内收入的影响。为了简化模型，需要对方程(8)做出一些假设。一种假设是假设长期中贸易条件(或者说国内外的相对物价水平)保持不变，那么就有(p-e-pf)=0和x=εz。于是可得：(9)(9)式意味着收支平衡约束下的产出增长率是出口增长率和资本流入增长率的加权平均。此外，还可以假设没有资本流入或者资本流入仅占从国外取得的收入的极小一部分，因而可以忽略不计。此时，θ=1，(8)式可简化如下：

表1中国GDP及出口增长率：1980—2010单位：%年份GDP增长率出口增长率年份GDP增长率出口增长率年份GDP增长率出口增长率19807.828.419919.223.9620029.123.3419815.218.27199214.214.8420031033.0619829.113.82199314-1.47200410.130.24198310.92.86199413.158.91200511.325.33198415.231.25199510.92.03200612.722.03198513.520.11199610-6.74200714.214.9219868.825.6119979.317.2720089.61.44198711.626.619987.81.2220099.2-17.59198811.31.1619997.67.6620101019.8619894.1-6.1720008.421.8719903.848.0620018.35.99(注：数据来源：《中国统计摘要2011》。出口增长率的数据是根据其中的历年出口额计算得来；增长率都是按不变价格计算的。)(10)(10)式表明，国内收入水平增长率由三个因素决定：进口和出口需求的价格弹性；长期贸易条件；进口和出口需求的收入弹性。在方程(10)加入长期贸易条件不变的假设，就可以得到：(11)根据(6)，又可得到：(12)方程(12)就是Thirlwall定律最简单的表达式，它是在没有资本净流入和长期中贸易条件不变两个假设前提下推导出来的。它表明有收支平衡约束下的长期产出增长率是由出口增长率和进口需求的收入弹性之比决定的，且如果π为常数，那么产出增长率就与出口增长率存在一一对应的关系。不过Thirlwall定律也受到较多的批评，比如，对长期中贸易条件稳定的假设，许多经济学家提出了质疑。还有，对于方程(12)中因果关系的方向，也有人提出了质疑。不过Thirlwall认为，长期中相对价格水平不变可能来自以下三个原因：一是一价定律；二是浮动汇率制度；三是寡头垄断的市场结构。而对于因果关系，Thirlwall遵循Kaldor的思想，认为需求是经济增长的最终决定力量，因此是来自国外的需求拉动本国经济增长，而不是经济增长促进出口。尽管如此，对于出口与经济增长之间的因果关系的方向的争论从未停休。理论上各执一词，实证结果也大相径庭。所以，对于出口与经济增长之间的因果关系的方向，本文没有必要深入讨论。许多文献证实了Thirlwall的理论，其中包括Atesoglu(1993)用美国数据的实证检验，Bairam(2001)对欧洲及北美19个国家数据的检验。三、模型设定与计量分析1、模型设定有必要陈述Thirlwall定律的假设在中国的符合性。第一，关于贸易条件稳定的假设。这个假设在中国1979—2010年间并不是成立的，但是这个条件实际上在各国都很难成立，且文献中也常常忽略这个假定，本文也采取相同的做法，不对这一假定做深入追究。第二，关于没有资本净流入的假定。这一假定在中国基本符合，因为在中国，每年的资本净流入相对出口而言几乎可以忽略不计。第三，关于出口必须快于进口的假定。这一假定在中国也符合。上文已经陈述，改革开放以来，中国出口年均增长17.23%，而进口年均增长16.37%。本文选取全国1980—2010年的时间序列数据，如表1所示。为了简化模型，本文假定进口需求的收入弹性π是一个常数，在样本期内保持不变。在这里还需强调的是，Thirlwall定律中所说的收入增长率与出口增长率之间的关系是长期中的关系，因此，如果直接用GDP增长率对出口增长率做二元线性回归，我们可能无法确定它们二者之间的关系。即使能得到它们之间的回归关系，结果也极有可能是错误的，因为我们必须得考虑时间序列相关的一系列问题。此外，由于出口增长率的波动性相对GDP增长率的波动性更大，直觉上我们就可以判断一年的GDP增长率与当年的出口增长率之间并不会有明显的联系。而且，我们的样本只有31年的数据，很可能不能解释长期中产出与出口之间的关系。在检验变量之间长期的关系时，Pesaran等(2001)提出一种叫做自回归分布滞后—非约束误差纠正模型(ARDL—UECM)的方法。这种方法在检验变量之间的长期关系时非常有效，且它的一个突出的优点是它允许解释变量都是I(0)或者I(1)，或者是二者的混合，只要被解释变量是I(1)。此外，它对于小样本而言，也相当有效。模型形式如下：(13)其中，y是因变量，△yt是y的一阶差分，xj是各个解释变量，△xj,t-i是各解释变量i期滞后的一阶差分。l和q是滞后期数，它们并不一定相等。用普通最小二乘法估计方程(13)。为了检验这些变量之间的长期关系，需要对方程(13)中所有x的滞后项系数都为0这个虚拟假设做检验。即：H0：βj=0，j=1，…，kH1：βj≠0，j=1，…，k(14)用F-检验对参数的总体显著性进行检验。但是这个检验的统计量并不是服从标准的F-分布，其临界值取决于变量是I(0)还是I(1)。不过Pesaran等计算并给出了这个统计量的临界值表。因此，我们可以方便地查询临界值。如果虚拟假设被拒绝，就说明变量之间存在协整关系，那么变量之间的协整系数就可以通过如下方式计算：pyxj=βj/(-β1)(15)即长期中，xj对y的影响系数为βj/(-β1)。对于本文所研究的收入增长率与出口增长率之间的长期关系，使用ARDL-UECM方法，我们建立如下模型：(16)其中，y表示GDP增长率，x表示出口增长率。如上文所述，还是用OLS估计这个模型，并检验一下虚拟假设：H0：β1=β2=0Hi：β1≠0，β2≠0(17)如果拒绝虚拟假设，则表明GDP增长率与出口增长率之间存在协整关系，则证明GDP增长率与出口增长率之间存在长期的相关关系。2、对Thirlwall定律的计量检验上文中已经指出，使用ARDL-UECM方法，要求被解释变量是I(1)，因此，我们需要首先对GDP增长率做一个简单的单位根检验。检验显示，GDP增长率确实存在单位根，也就是说是I(1)。此外，我们需要选择合理的滞后项数，即l和q的值。根据AIC和SIC信息准则，本文选择1=1和q=2，即选择如下模型：△yt=β0+β1yt-1+β2xt-1+b11△yt-1+b20△x+b21△xt-1+b22△xt-2+ut(18)回归结果如表2所示。注意到，表2显示F=4.41。查Pesaran给出的临界值表可知，在1%的显著性水平上，两个临界值分别是6.84和7.84(临界值表见Pesaranetal.Boundstestapproachestotheanalysisoflevelrelationships.JournalofAppliedEconometrics，May/Jun，2001，p300.TableCI(iii)。本模型中，k=1。)，F=4.41落在临界值之外，因此，我们可以拒绝虚拟假设，即拒绝变量之间不存在协整关系。也就是说，结果表明，GDP增长率与出口增长率之间存在很强的相关关系。此外，根据上文等式(15)，可以计算出产出增长率与出口增长率之间的相关系数为0.133/0.756≈0.18。因此，相关方程可以表示如下：y=0.18x(19)(2.12)上式中，括号中的数字是系数的t值，这个t值就是表1中变量x(-1)的系数的t值。t值显示系数0.18在5%的显著性水平下是显著的。

表2GDP与出口之间的长期关系的检验解释变量被解释变量：产出增长率的一阶差分(D(y))常数项5.51(3.01)***y(-1)-0.756(--4.29)***x(-1)0.133(2.12)**D(y(-1))0.452(2.75)**D(x)0.046(1.89)*D(x(-1))-0.058(-1.31)D(x(-2))-0.024(-0.86)样本量31调整后的R20.43F统计量4.41(注：括号中的数字表示t值；**和***分别表示在5%和1%的显著性水平显著。)以上结果表明，中国GDP增长率和出口增长率之间确实存在很强的正相关关系。因此，可以说明，Thirlwall定律在中国适用，即长期中，收入增长率与出口增长率正相关，出口增长10%，将推动总产出增长1.8%。这个值明显大于林毅夫和李XX2003年估计的1%，这可能表明他们的估计方法存在的缺陷确实对结果产生了较大的影响。林XX和李XX的方法所关心的是出口增加通过刺激消费、投资、政府支出来间接地影响我国的GDP的增长，而没有考虑出口增长—因而产出增长—对生产率的促进作用。这可能就是导致林和李XX估计的结果偏低的原因。四、结论本文通过ARDL-UECM方法分析，证实了中国经济增长与出口增长之间的相关关系，验证了Thirlwall定律在中国的适用性，且表明1978—2010年间，出口增长10%，收入将增长1.8%，不止是林毅夫和李XX2003年估计的1%。这意味着，为了维持我国经济的快速增长，继续发挥比较优势，保持出口的稳定增长意义重大。

【参考文献】[1]Thirlwall,A.P..Theinteractionbetweenincomeandexpenditureintheabsorptionapproachtothebalanceofpayments[J].JournalofMacroeconomics,1979,vol.1(2).[2]Thilwall,A.P..APlainMan'sGuidetoKaldor'sGrowthLaws[J].JournalofPost-KeynesianEconomics,1983,5(3).[3]Thilwall,A.P..GrowthandDevelopment:WithSpecialReferencetoDevelopingEconomies[M].7thedition.NewYork:PalgraveMacmillan,2003.[4]Feder,G.,.OnExportandEconomicGrowth[J].JournalofDevelopmentEconomics,1983(12).[5]庄佳强、徐长生：论出口、消费与经济增长[J].国际贸易问题，2008(10).[6]Jeon,Yongbok..EconomicGrowthinChina,1978-2004:AKaldorianApproach[D].TheUniversityof[7]林毅夫、李XX：出口与中国的经济增长：需求导向的分析[J].经济学(季刊)，2003(7).[8]Kaldor,N..AModelofEconomicGrowth[J].EconomicJournal,1957,57(268).[9]Atesoglu,L..ManufacturingandEconomicGrowthintheUnitedStates[J].ApliedEconomics,1993(6).[10]Bairam,Erkin.Thirlwall'slawandthestabilityofexportandimportincomeelasticity[J].InternationalReviewofAppliedEconomics,2001,vol.15,No.3.[11]Pesaran,Hashem,etal..Boundstestapproachestotheanalysisoflevelrelationships[J].JournalofAppliedEconometrics,2001(May/June).本科毕业设计外文文献及译文文献、资料题目：TMS320C5402文献、资料来源：文献、资料发表（出版）日期：院（部）：信息与电气工程学院专业：班级：姓名：学号：指导教师：翻译日期：9---外文文献TMS320C5402AdvancedMultibusArchitectureWithThreeSeparate16-BitDataMemoryBusesandOneProgramMemoryBus.40-BitArithmeticLogicUnit(ALU),Includinga40-BitBarrelShifterandTwoIndependent40-BitAccumulators1717-BitParallelMultiplierCoupledtoa40-BitDedicatedAdderforNon-PipelinedSingle-CycleMultiply/Accumulate(MAC)Operation.Compare,Select,andStoreUnit(CSSU)fortheAdd/CompareSelectionoftheViterbiOperator.ExponentEncodertoComputeanExponentValueofa40-BitAccumulatorValueinaSingleCycle.TwoAddressGeneratorsWithEightAuxiliaryRegistersandTwoAuxiliaryRegisterArithmeticUnits(ARAUDataBusWithaBus-HolderFeature.ExtendedAddressingModefor1M16-BitMaximumAddressableExternalProgramSpace.4Kx16-BitOn-ChipROM.16Kx16-BitDual-AccessOn-ChipRAM.Single-Instruction-RepeatandBlock-RepeatOperationsforProgramCode.Block-Memory-MoveInstructionsforEfficientProgramandDataManagement.InstructionsWitha32-BitLongWordOperand.InstructionsWithTwo-orThree-OperandReads.ArithmeticInstructionsWithParallelStoreandParallelLoad.ConditionalStoreInstructionsFastReturnFromInterruptOn-ChipPeripheralsSoftware-ProgrammableWait-StateGeneratorandProgrammableBankSwitchingOn-ChipPhase-LockedLoop(PLL)ClockGeneratorWithInternalOscillatororExternalClockSource.TwoMultichannelBufferedSerialPorts(McBSPs).Enhanced8-BitParallelHost-PortInterface(HPI8).Two16-BitTimers,Six-ChannelDirectMemoryAccess(DMA)Controller.PowerConsumptionControlWithIDLE1,IDLE2,andIDLE3InstructionsWithPower-DownModes.CLKOUTOffControltoDisableCLKOUTOn-ChipScan-BasedEmulationLogic,IEEEStd1149.1†(JTAG)BoundaryScanLogic10-nsSingle-CycleFixed-PointInstructionExecutionTime(100MIPS)for3.3-VPowerSupply(1.8-VCore).Availableina144-PinPlasticLow-ProfileQuadFlatpack(LQFP)(PGESuffix)anda144-PinBallGridArray(BGA)(GGUSuffix).1.descriptionTheTMS320VC5402fixed-point,digitalsignalprocessor(DSP)(hereafterreferredtoasthe’5402unlessotherwisespecified)isbasedonanadvancedmodifiedHarvardarchitecturethathasoneprogrammemorybusandthreedatamemorybuses.Thisprocessorprovidesanarithmeticlogicunit(ALU)withahighdegreeofparallelism,application-specifichardwarelogic,on-chipmemory,andadditionalon-chipperipherals.ThebasisoftheoperationalflexibilityandspeedofthisDSPisahighlyspecializedinstructionset.Separateprogramanddataspacesallowsimultaneousaccesstoprograminstructionsanddata,providingthehighdegreeofparallelism.Tworeadoperationsandonewriteoperationcanbeperformedinasinglecycle.Instructionswithparallelstoreandapplication-specificinstructionscanfullyutilizethisarchitecture.Inaddition,datacanbetransferredbetweendataandprogramspaces.Suchparallelismsupportsapowerfulsetofarithmetic,logic,andbit-manipulationoperationsthatcanbeperformedinasinglemachinecycle.Inaddition,the’5402includesthecontrolmechanismstomanageinterrupts,repeatedoperations,andfunctioncalls.2.memoryThe’5402deviceprovidesbothon-chipROMandRAMmemoriestoaidinsystemperformanceandintegration.3.on-chipROMwithbootloaderThe’5402featuresa4K-word16-biton-chipmaskableROM.CustomerscanarrangetohavetheROMofthe’5402programmedwithcontentsuniquetoanyparticularapplication.AsecurityoptionisavailabletoprotectacustomROM.ThissecurityoptionisdescribedintheTMS320C54xDSPCPUandPeripheralsReferenceSet,Volume1(literaturenumberSPRU131).NotethatonlytheROMsecurityoption,andnottheROM/RAMoption,isavailableonthe’5402.Abootloaderisavailableinthestandard’5402on-chipROM.Thisbootloadercanbeusedtoautomaticallytransferusercodefromanexternalsourcetoanywhereintheprogrammemoryatpowerup.IftheMP/MCpinissampledlowduringahardwarereset,executionbeginsatlocationFF80hoftheon-chipROM.Thislocationcontainsabranchinstructiontothestartofthebootloaderprogram.Thestandard’5402bootloaderprovidesdifferentwaystodownloadthecodetoaccomodatevarioussystemrequirements:（1）Parallelfrom8-bitor16-bit-wideEPROM（2）ParallelfromI/Ospace8-bitor16-bitmode（3）Serialbootfromserialports8-bitor16-bitmode（4）Host-portinterfacebootThestandardon-chipROMlayoutisshown4.on-chipRAMThe’5402devicecontains16K16-bitofon-chipdual-accessRAM(DARAM).TheDARAMiscomposedoftwoblocksof8Kwordseach.EachblockintheDARAMcansupporttworeadsinonecycle,orareadandawriteinonecycle.TheDARAMislocatedintheaddressrange0060h–3FFFhindataspace,andcanbemappedintoprogram/dataspacebysettingtheOVLYbittoone.5.relocatableinterruptvectortableThereset,interrupt,andtrapvectorsareaddressedinprogramspace.Thesevectorsaresoft—meaningthattheprocessor,whentakingthetrap,loadstheprogramcounter(PC)withthetrapaddressandexecutesthecodeatthevectorlocation.Fourwordsarereservedateachvectorlocationtoaccommodateadelayedbranchinstruction,eithertwo1-wordinstructionsorone2-wordinstruction,whichallowsbranchingtotheappropriateinterruptserviceroutinewithminimaloverhead.Atdevicereset,thereset,interrupt,andtrapvectorsaremappedtoaddressFF80hinprogramspace.However,thesevectorscanberemappedtothebeginningofany128-wordpageinprogramspaceafterdevicereset.Thisisdonebyloadingtheinterruptvectorpointer(IPTR)bitsinthePMSTregister(seeFigure2)withtheappropriate128-wordpageboundaryaddress.AfterloadingIPTR,anyuserinterruptortrapvectorismappedtothenew128-wordpage.NOTE:Thehardwarereset(RS)vectorcannotberemappedbecauseahardwareresetloadstheIPTRwith1s.Therefore,theresetvectorisalwaysfetchedatlocationFF80hinprogramspace.6.ProcessorModeStatus(PMST)RegistersextendedprogrammemoryThe’5402usesapagedextendedmemoryschemeinprogramspacetoallowaccessofupto1024Kprogrammemorylocations.Inordertoimplementthisscheme,the’5402includesseveralfeaturesthatarealsopresentonthe’548/’549devices:Twentyaddresslines,insteadofsixteenAnextramemory-mappedregister,theXPCregister,definesthepageselection.Thisregisterismemory-mappedintodataspacetoaddress001Eh.Atahardwarereset,theXPCisinitializedto0.Sixextrainstructionsforaddressingextendedprogramspace.ThesesixinstructionsaffecttheXPC.FB[D]pmad(20bits)–FarbranchFBACC[D]Accu[19:0]–FarbranchtothelocationspecifiedbythevalueinaccumulatorAoraccumulatorBFCALL[D]pmad(20bits)–FarcallFCALA[D]Accu[19:0]–FarcalltothelocationspecifiedbythevalueinaccumulatorAoraccumulatorBFRET[D]–FarreturnFRETE[D]–FarreturnwithinterruptsenabledInadditiontothesenewinstructions,two’54xinstructionsareextendedtouse20bitsinthe’5402:READAdata_memory(using20-bitaccumulatoraddress).WRITAdata_memory(using20-bitaccumulatoraddress)Allotherinstructions,softwareinterruptsandhardwareinterruptsdonotmodifytheXPCregisterandaccessonlymemorywithinthecurrentpage.Programmemoryinthe’5402isorganizedinto16pagesthatareeach64Kinlength,asshowninFigure3.7.on-chipperipheralsThe’5402devicehasthefollowingperipherals:Software-programmablewait-stategeneratorwithprogrammablebank-switchingwaitstates.（1）Anenhanced8-bithost-portinterface(HPI8).（2）Twomultichannelbufferedserialports(McBSPs).（3）Twohardwaretimers.（4）Aclockgeneratorwithaphase-lockedloop(PLL).（5）Adirectmemoryaccess(DMA)controller.8.software-programmablewait-stategeneratorThesoftwarewait-stategeneratorofthe’5402canextendexternalbuscyclesbyuptofourteenmachinecycles.DevicesthatrequiremorethanfourteenwaitstatescanbeinterfacedusingthehardwareREADYline.Whenallexternalaccessesareconfiguredforzerowaitstates,theinternalclockstothewait-stategeneratorareautomaticallydisabled.Disablingthewait-stategeneratorclocksreducesthepowercomsumptionofthe’5402.Thesoftwarewait-stateregister(SWWSR)controlstheoperationofthewait-stategenerator.The14LSBsoftheSWWSRspecifythenumberofwaitstates(0to7)tobeinsertedforexternalmemoryaccessestofiveseparateaddressranges.Thisallowsadifferentnumberofwaitstatesforeachofthefiveaddressranges.Additionally,thesoftwarewait-statemultiplier(SWSM)bitofthesoftwarewait-statecontrolregister(SWCR)definesamultiplicationfactorof1or2forthenumberofwaitstates.Atreset,thewait-stategeneratorisinitializedtoprovidesevenwaitstatesonallexternalmemoryaccesses.9.parallelI/OportsThe’5402hasatotalof64KI/Oports.TheseportscanbeaddressedbythePORTRinstructionorthePORTWinstruction.TheISsignalindicatesaread/writeoperationthroughanI/Oport.The’5402caninterfaceeasilywithexternaldevicesthroughtheI/Oportswhilerequiringminimaloff-chipaddress-decodingcircuits.10.enhanced8-bithost-portinterfaceThe’5402host-portinterface,alsoreferredtoastheHPI8,isanenhancedversionofthestandard8-bitHPIfoundonearlier’54xDSPs(’542,’545,’548,and’549).TheHPI8isan8-bitparallelportforinterprocessorcommunication.ThefeaturesoftheHPI8include:Standardfeatures:Sequentialtransfers(withautoincrement)orrandom-accesstransfers，Hostinterruptand’54xinterruptcapability，MultipledatastrobesandcontrolpinsforinterfaceflexibilityEnhancedfeaturesofthe’5402HPI8:Accesstoentireon-chipRAMthroughDMAbus；Capabilitytocontinuetransferringduringemulationstop；TheHPI8functionsasaslaveandenablesthehostprocessortoaccesstheon-chipmemoryofthe’5402.Amajorenhancementtothe’5402HPIoverpreviousversionsisthatitallowshostaccesstotheentireon-chipmemoryrangeoftheDSP.TheHPI8memorymapisidenticaltothatoftheDMAcontrollershowninFigure7.ThehostandtheDSPbothhaveaccesstotheon-chipRAMatalltimesandhostaccessesarealwayssynchronizedtotheDSPclock.IfthehostandtheDSPcontendforaccesstothesamelocation,thehosthaspriority,andtheDSPwaitsforoneHPI8cycle.Notethatsincehostaccessesarealwayssynchronizedtothe’5402clock,anactiveinputclock(CLKIN)isrequiredforHPI8accessesduringIDLEstates,andhostaccessesarenotallowedwhilethe’5402resetpinisasserted.TheHPI8interfaceconsistsofan8-bitbidirectionaldatabusandvariouscontrolsignals.Sixteen-bittransfersareaccomplishedintwopartswiththeHBILinputdesignatinghighorlowbyte.ThehostcommunicateswiththeHPI8throughthreededicatedregisters—HPIaddressregister(HPIA),HPIdataregister(HPID),andanHPIcontrolregister(HPIC).TheHPIAandHPIDregistersareonlyaccessiblebythehost,andtheHPICregisterisaccessiblebyboththehostandthe’5402.11.multichannelbufferedserialportsThe’5402deviceincludestwohigh-speed,full-duplexmultichannelbufferedserialports(McBSPs)thatallowdirectinterfacetoother’C54x/’LC54xdevices,codecs,andotherdevicesinasystem.TheMcBSPsarebasedonthestandardserialportinterfacefoundonother’54xdevices.Likeitspredecessors,theMcBSPprovides:Full-duplexcommunication；Double-buffereddataregisters,whichallowacontinuousdatastream；Independentframingandclockingforreceiveandtransmit。Inaddition,theMcBSPhasthefollowingcapabilities:Directinterfaceto:T1/E1framers；MVIPswitchingcompatibleandST-BUScompliantdevices；IOM-2compliantdevices；Serialperipheralinterfacedevices；Multichanneltransmitandreceiveofupto128channels；Awideselectionofdatasizesincluding8,12,16,20,24,or32bits；-lawandA-lawcompanding；Programmablepolarityforbothframesynchronizationanddataclocks；Programmableinternalclockandframegeneration。TheMcBSPsconsistofseparatetransmitandreceivechannelsthatoperateindependently.TheexternalinterfaceofeachMcBSPconsistsofthefollowingpins:BCLKXTransmitreferenceclock；BDXTransmitdata；BFSXTransmitframesynchronization；BCLKRReceivereferenceclock；BDRReceivedata；BFSRReceiveframesynchronization。Thesixpinslistedarefunctionallyequivalenttopreviousserialportinterfacepinsinthe’C5000familyofDSPs.Onthetransmitter,transmitframesynchronizationandclockingareindicatedbytheBFSXandBCLKXpins,respectively.TheCPUorDMAcaninitiatetransmissionofdatabywritingtothedatatransmitregister(DXR).DatawrittentoDXRisshiftedoutontheBDXpinthroughatransmitshiftregister(XSR).ThisstructureallowsDXRtobeloadedwiththenextwordtobesentwhilethetransmissionofthecurrentwordisinprogress.12.multichannelbufferedserialports(continued)Onthereceiver,receiveframesynchronizationandclockingareindicatedbytheBFSRandBCLKRpins,respectively.TheCPUorDMAcanreadreceiveddatafromthedatareceiveregister(DRR).DatareceivedontheBDRpinisshiftedintoareceiveshiftregister(RSR)andthenbufferedinthereceivebufferregister(RBR).IftheDRRisempty,theRBRcontentsarecopiedintotheDRR.Ifnot,theRBRholdsthedatauntiltheDRRisavailable.Thisstructureallowsstorageofthetwopreviouswordswhilethereceptionofthecurrentwordisinprogress.TheCPUandDMAcanmovedatatoandfromtheMcBSPsandcansynchronizetransfersbasedonMcBSPinterrupts,eventsignals,andstatusflags.TheDMAiscapableofhandlingdatamovementbetweentheMcBSPsandmemorywithnointerventionfromtheCPU.Inadditiontothestandardserialportfunctions,theMcBSPprovidesprogrammableclockandframesynchronizationsignals.Theprogrammablefunctionsinclude:Framesynchronizationpulsewidth；Frameperiod；Framesynchronizationdelay；Clockreference(internalvs.external)；Clockdivision；Clockandframesynchronizationpolarity；Theon-chipcompandinghardwareallowscompressionandexpansionofdataineitherlaworA-lawformat.Whencompandingisused,transmitdataisencodedaccordingtospecifiedcompandinglawandreceiveddataisdecodedto2scomplementformat.TheMcBSPallowsthemultiplechannelstobeindependentlyselectedforthetransmitterandreceiver.Whenmultiplechannelsareselected,eachframerepresentsatime-divisionmultiplexed(TDM)datastream.InusingTDMdatastreams,theCPUmayonlyneedtoprocessafewofthem.Thus,tosavememoryandbusbandwidth,multichannelselectionallowsindependentenablingofparticularchannelsfortransmissionandreception.Upto32channelsinastreamofupto128channelscanbeenabled.Theclock-stopmode(CLKSTP)intheMcBSPprovidescompatibilitywiththeserialperipheralinterface(SPI)protocol.ThewordsizessupportedbytheMcBSPareprogrammablefor8-,12-,16-,20-,24-,or32-bitoperation.WhentheMcBSPisconfiguredtooperateinSPImode,boththetransmitterandthereceiveroperatetogetherasamasterorasaslave.TheMcBSPisfullystaticandoperatesatarbitrarilylowclockfrequencies.ThemaximumfrequencyisCPUclockfrequencydividedby2.13.hardwaretimerThe’5402devicefeaturestwo16-bittimingcircuitswith4-bitprescalers.ThemaincounterofeachtimerisdecrementedbyoneeveryCLKOUTcycle.Eachtimethecounterdecrementsto0,atimerinterruptisgenerated.Thetimerscanbestopped,restarted,reset,ordisabledbyspecificcontrolbits.14.clockgeneratorTheclockgeneratorprovidesclockstothe’5402device,andconsistsofaninternaloscillatorandaphase-lockedloop(PLL)circuit.Theclockgeneratorrequiresareferenceclockinput,whichcanbeprovidedbyusingacrystalresonatorwiththeinternaloscillator,orfromanexternalclocksource。15.clockgenerator(continued)Thereferenceclockinputisthendividedbytwo(DIVmode)togenerateclocksforthe’5402device,orthePLLcircuitcanbeused(PLLmode)togeneratethedeviceclockbymultiplyingthereferenceclockfrequencybyascalefactor,allowinguseofaclocksourcewithalowerfrequencythanthatoftheCPU.ThePLLisanadaptivecircuitthat,oncesynchronized,locksontoandtracksaninputclocksignal.WhenthePLLisinitiallystarted,itentersatransitionalmodeduringwhichthePLLacquireslockwiththeinputsignal.OncethePLLislocked,itcontinuestotrackandmaintainsynchronizationwiththeinputsignal.Then,otherinternalclockcircuitryallowsthesynthesisofnewclockfrequenciesforuseasmasterclockforthe’5402device.Thisclockgeneratorallowssystemdesignerstoselecttheclocksource.Thesourcesthatdrivetheclockgeneratorare:Acrystalresonatorcircuit.ThecrystalresonatorcircuitisconnectedacrosstheX1andX2/CLKINpinsofthe’5402toenabletheinternaloscillator.Anexternalclock.TheexternalclocksourceisdirectlyconnectedtotheX2/CLKINpin,andX1isleftunconnected.NOTE:Allrevisionsofthe’5402canbeoperatedwithanexternalclocksource,providedthatthepropervoltagelevelsbedrivenontheX2/CLKINpin.ItshouldbenotedthattheX2/CLKINpinisreferencedtothedevice1.8Vpowersupply(CVdd),ratherthanthe3VI/Osupply(DVdd).RefertotherecommendedoperatingconditionssectionofthisdocumentfortheallowablevoltagelevelsoftheX2/CLKINpin.Thesoftware-programmablePLLfeaturesahighlevelofflexibility,andincludesaclockscalerthatprovidesvariousclockmultiplierratios,capabilitytodirectlyenableanddisablethePLL,andaPLLlocktimerthatcanbeusedtodelayswitchingtoPLLclockingmodeofthedeviceuntillockisachieved.Devicesthathaveabuilt-insoftware-programmablePLLcanbeconfiguredinoneoftwoclockmodes:PLLmode.Theinputclock(X2/CLKIN)ismultipliedby1of31possibleratios.TheseratiosareachievedusingthePLLcircuitry.DIV(divider)mode.Theinputclockisdividedby2or4.NotethatwhenDIVmodeisused,thePLLcanbecompletelydisabledinordertominimizepowerdissipation.Thesoftware-programmablePLLiscontrolledusingthe16-bitmemory-mapped(address0058h)clockmoderegister(CLKMD).TheCLKMDregisterisusedtodefinetheconfigurationofthePLLclockmodule.Uponreset,theCLKMDregisterisinitializedwithapredeterminedvaluedependentonlyuponthestateoftheCLKMD1,CLKMD3pinsasshowninTable5.16.DMAcontrollerThe’5402directmemoryaccess(DMA)controllertransfersdatabetweenpointsinthememorymapwithoutinterventionbytheCPU.TheDMAcontrollerallowsmovementsofdatatoandfrominternalprogram/datamemoryorinternalperipherals(suchastheMcBSPs)tooccurinthebackgroundofCPUoperation.TheDMAhassixindependentprogrammablechannelsallowingsixdifferentcontextsforDMAoperation.17.featuresTheDMAhasthefollowingfeatures:TheDMAoperatesindependentlyoftheCPU._TheDMAhassixchannels.TheDMAcankeeptrackofthecontextsofsixindependentblocktransfers.TheDMAhashigherprioritythantheCPUforinternalaccesses.Eachchannelhasindependentlyprogrammablepriorities.Eachchannel’ssourceanddestinationaddressregisterscanhaveconfigurableindexesthroughmemoryoneachreadandwritetransfer,respectively.Theaddressmayremainconstant,bepost-incremented,post-decremented,orbeadjustedbyaprogrammablevalue.Eachreadorwritetransfermaybeinitializedbyselectedevents.Uponcompletionofahalf-blockoranentire-blocktransfer,eachDMAchannelmaysendaninterrupttotheCPU.TheDMA