设计参考源码手册1746个zhcs132d

ZHCS132D–MARCH2011–REVISEDJANUARY特 说 无引线小外形尺寸(SON56

5×6毫米的小巧米封 俯视83836457(Pin12POLDC-DCIMVP、VRMVRD

EfficiencyEfficiency

65PowerPowerLoss321 OutputCurrentPleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddierstheretoappearsattheendofthisdatasheet.Copyright©2011–2012,TexasInstrumentsNexFETisaCopyright©2011–2012,TexasInstrumentsPRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheInstrumentsstandardwarranty.Productionprocessingdoes EnglishDataSheet:necessarilyincludetestingofallThesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedevicecedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. UMTA=25°C(unlessotherwisenoted)VoltageVINto-0.8toVTGto-8toVBGto-8toVPulsedCurrentRating,APowerDissipation,WAvalancheEnergySyncFET,ID=87A,L=ControlFET,ID=44A,L=OperatingJunctionandStorageTemperatureRange,TJ,-55to(1)StressesbeyondthoselistedunderAbsoluteumRatingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedisnotimplied.Exposuretoabsolute-um-ratedconditionsforextendedperiodsmayaffectdevicereliability.MENDEDOPERATINGTA=25°(unlessotherwise GateDriveVoltage, VInputSupplyVoltage,VSwitchingFrequency,CBST=0.1μF OperatingAOperatingTemperature,POWERBLOCKTA=25°(unlessotherwise PowerLoss,PLOSSVN=12V,VGS=5V,VOUT=1.3V,IOUT=20A,fSW=500kHz,LOUT=0.3µH,TJ=WVINQuiescentCurrent,TGtoTGR=0VBGtoPGND=(1)Measurementmadewithsix10µF(TDKC3216X5R1C106KTorequivalent)ceramiccapacitorscedacrossVINtoPGNDpinsandusingahighcurrent5VdriverIC.THERMALTA=25°C(unlessotherwiseTHERMAL toambient(MinCu)toambient(MaxCu)tocase(Topofpackage)tocase(PGNDPin)DevicemountedonFR4materialwith1-inch2(6.45-cm2)RθJCisdeterminedwiththedevicemountedona1-inch2(6.45-cm2),2oz.(0.071-mmthick)Cupadona1.5-inch×1.5-(3.81-cm×3.81-cm),0.06-inch(1.52-mm)thickFR4board.RθJCisspecifiedbydesignwhileRθJAisdeterminedbytheuser’sboardELECTRICALTA=25°C(unlessotherwiseTESTQ1ControlQ2SyncStaticDraintoSourceVGS=0V,IDS=VVGS=0V,VDS=11VDS=0V,VGS=+10/-VDS=VGS,IDS=VZDS(on)EffectiveACVIN=12V,VGS=5V,VOUT=1.3V,IOUT=20A,fSW=500kHz,LOUT=VDS=15V,IDS=SDynamic InputVGS=0V,VDS=f=OutputSeriesGate12ΩGateChargeTotalVDS=15V,IDS=20AGateCharge-GatetoGateCharge-GatetoGateChargeat2OutputVDS=9.8V,VGS=TurnOnDelayVDS=15V,VGS=4.5V,IDS=20A,RG=2ΩRiseTurnOffDelayFallDiode DiodeForwardIDS=20A,VGS= VReverseRecoveryVdd=9.8V,IF=di/dt=ReverseRecoveryEquivalentSystemPerformancebasedonapplicationtesting.Seepage9forMaxRθJA= MaxRθJA=whenmounted whenmounted1inch2(6.45cm2) minimumpadarea2-oz.(0.071- 2-oz.(0.071-mmNthick)NTYPICALPOWERBLOCKDEVICETJ=125°C,unlessstatedVINVIN=12VVGS=5VVOUT=1.3VfSW=500kHzLOUT=98PowerPowerLoss6543210 OutputCurrent

VINVIN=12VVGS=5VVOUT=1.3VfSW=500kHzLOUT=PowerPowerLoss,1

JuncionTemperatureFigure1.PowerLossvsOutput Figure2.NormalizedPowerLossvsVIN=12VVIN=12VVGS=5VVOUT=1.3VfSW=500kHzLOUT=Nat OutputCurrentOutputCurrentOutputCurrent AmbientTemperature

0

AmbientTemperatureFigure3.SafeOperatingArea–PCBVertical Figure4.SafeOperatingArea–PCBHorizontalVINVIN=12VVGS=5VVOUT=13VfSW=500kHzLOUT=OutputOutputCurrent BoardTemperatureFigure5.TypicalSafeOperatingTheTypicalPowerBlockSystemCharacteristiccurvesarebasedonmeasurementsmadeonaPCBdesignwithdimensionsof4.0”(W)×3.5”(L)x0.062”(H)and6copperlayersof1oz.copperthickness.SeeApplicationSectionfordetailedexnation.TYPICALPOWERBLOCKDEVICECHARACTERISTICS(TJ=125°C,unlessstatedPowerPowerLoss,1

14VV=12VV=5VV=1.3VL=0.3µHI=35A

PowerPowerLoss,1

14VV=5VV=1.3VL=0.3µHf=500kHzI=35ASOASOATemperatureAdjSOASOATemperatureAdj200350

650800950110012501400SwitchingFrequency

0.6 InputVoltageFigure6.NormalizedPowerLossvsSwitching Figure7.NormalizedPowerLossvsInputVV=12VV=f=500kHzL=0.3µHI=35APowerPowerLoss,1 2 OutputVoltage

140

PowerPowerLoss,1

VV=12VV=5VV=1.3VI=35ASOATemperatureAdj00.10.20.30.40.50.60.708SOATemperatureAdjOutputInductance

14SOASOATemperatureAdj0Figure8.NormalizedPowerLossvs.Output Figure9.NormalizedPowerLossvs.OutputTYPICALPOWERBLOCKMOSFETTA=25°C,unlessstatedVGS=VGS=8.0VVGS=4.5VVGS=IDS-IDS-Drain-to-SourceCurrent-IDS-Drain-to-SourceCurrent- 0 8VDS-Drain-to-SourceVoltage-Figure10.ControlMOSFET

0 0 0VDS-Drain-to-SourceVoltage-Figure11.SyncMOSFETTC=TC=125°CTC=25°CTC=−55°CVDS=IDS-IDS-Drain-to-SourceCurrent-IDS-Drain-to-SourceCurrent- 0 0

VGS-Gate-to-SourceVoltage-

VGS-Gate-to-SourceVoltage-

2Figure12.ControlMOSFET Figure13.SyncMOSFETID=20AID=20AVDD=15VVGS-VGS-Gate-to-SourceVoltageVGS-Gate-to-SourceVoltage 0 Qg-GateCharge-nCFigure14.ControlMOSFETGate

0 Qg-GateCharge-nCFigure15.SyncMOSFETGateTYPICALPOWERBLOCKMOSFETCHARACTERISTICS(TA=25°C,unlessstatedCiss=CgdCiss=Cgd+CgsCoss=Cds+CgdCrss=Cgdf=1MHzVGS=C−CapacitanceC−Capacitance−C−Capacitance− 0 0

VDS-Drain-to-SourceVoltage-

VDS-Drain-to-SourceVoltage-Figure16.ControlMOSFET Figure17.SyncMOSFETID=ID=VGSthVGSth-ThresholdVoltage-VGSth-ThresholdVoltage- −75−50 75100125150TC-CaseTemperature-Figure18.ControlMOSFET

0−75−50 75100125150TC-CaseTemperature-Figure19.SyncMOSFETIDID=TC=125°CTC=25ºC--RDSRDSon-On- VGS-Gate-to-SourceVoltage-Figure20.ControlMOSFETRDS(on)vs

IDID=TC=125°CTC=25ºC-876RDSRDSon-On-43210 VGS-Gate-to-SourceVoltage-Figure21.SyncMOSFETRDS(on)vsTYPICALPOWERBLOCKMOSFETCHARACTERISTICS(TA=25°C,unlessstatedIDID=20AVGS=NormalizedNormalizedOn-0−75−50 75100125150TC-CaseTemperature-Figure22.ControlMOSFETNormalized

IDID=20AVGS=NormalizedNormalizedOn-0−75−50 75100125150TC-CaseTemperature-Figure23.SyncMOSFETNormalizedTC=TC=125°CTC=25°CISD−ISD−Source-to-DrainCurrent-ISD−Source-to-DrainCurrent- 0 0

VSD−Source-to-DrainVoltage-

VSD−Source-to-DrainVoltage-Figure24.ControlMOSFETBody Figure25.SyncMOSFETBodyTC=25°CTCTC=25°CTC=125°CIAV-PeakAvalancheCurrent-IAV-PeakAvalancheCurrent- 1 tAV-TimeinAvalanche-

1 tAV-TimeinAvalanche-Figure26.ControlMOSFETUnclampedInductive Figure27.SyncMOSFETUnclampedInductiveSwitchingAPPLICATIONEquivalentSystemManyoftoday’shighperformancecomputingsystemsrequirelowpowerconsumptioninanefforttoreducesystemoperatingtemperaturesandimproveoverallsystemefficiency.Thishascreatedamajoremphasisonimprovingtheconversionefficiencyoftoday’sSynchronousBuckTopology.Inparticular,therehasbeenanemphasisinimprovingtheperformanceofthecriticalPowerSemiconductorinthePowerStageofthisApplication(seeFigure28).Assuch,optimizationofthepowersemiconductorsintheseapplications,needstogobeyondsimplyreducingRDS(ON).FigureTheCSD87351Q5DispartofTI’sPowerBlockproductfamilywhichisahighlyoptimizedproductforuseinasynchronousbucktopologyrequiringhighcurrent,highefficiency,andhighfrequency.ItincorporatesTI’slatestgenerationsiliconwhichhasbeenoptimizedforswitchingperformance,aswellasminimizinglossesassociatedwithQGD,QGS,andQRR.Furthermore,TI’spatentedpackagingtechnologyhasminimizedlossesbynearlyeliminatingparasiticelementsbetweentheControlFETandSyncFETconnections(seeFigure29).AkeychallengesolvedbyTI’spatentedpackagingtechnologyisthesystemlevelimpactofCommonSourceInductance(CSI).CSIgreatlyimpedestheswitchingcharacteristicsofanyMOSFETwhichinturnincreasesswitchinglossesandreducessystemefficiency.Asaresult,theeffectsofCSIneedtobeconsideredduringtheMOSFETselectionprocess.Inaddition,standardMOSFETswitchinglossequationsusedtopredictsystemefficiencyneedtobemodifiedinordertoaccountfortheeffectsofCSI.FurtherdetailsbehindtheeffectsofCSIandmodificationofswitchinglossequationsareoutlinedinTI’sApplicationNoteSLPA–009.FigureThecombinationofTI’slatestgenerationsiliconandoptimizedpackagingtechnologyhascreatedabenarkingsolutionthatoutperformsindustrystandardMOSFETchipsetsofsimilarRDS(ON)andMOSFETchipsetswithlowerRDS(ON).Figure30andFigure31comparetheefficiencyandpowerlossperformanceoftheCSD87351Q5DversusindustrystandardMOSFETchipsetscommonlyusedinthistypeofapplication.Thiscomparisonpurelyfocusesontheefficiencyandgeneratedlossofthepowersemiconductorsonly.TheperformanceofCSD87351Q5DclearlyhighlightstheimportanceofconsideringtheEffectiveACOn-Impedance(ZDS(ON))duringtheMOSFETselectionprocessofanynewdesign.SimplynormalizingtotraditionalMOSFETRDS(ON)specificationsisnotanindicatoroftheactualin-circuitperformancewhenusingTI’sPowerBlockVGSVGS=5VVIN=12VVOUT=1.3VLOUT=0.3µHfSW=500kHzTA=25ºCPowerBlockHS/LSRDSON=7.4m/2.6mDiscreteHS/LSRDSON=7.4m/2.6mDiscreteHS/LSRDSON=7.4m/1.6mEfficiencyEfficiency OutputCurrentFigure

PowerBlockPowerBlockHS/LSRDSON=7.4m/2.6mDiscreteHS/LSRDSON=7.4m/2.6mDiscreteHS/LSRDSON=7.4m/1.6mVGS=5VVIN=12VVOUT=1.3VLOUT=0.3µHfSW=500kHzTA=25ºC5PowerPowerLoss3210 OutputCurrentFigureThechartbelowcomparesthetraditionalDCmeasuredRDS(ON)ofCSD87351Q5DversusitsZDS(ON).ThiscomparisontakesintoaccounttheimprovedefficiencyassociatedwithTI’spatentedpackagingtechnology.Assuch,whencomparingTI’sPowerBlockproductstoindividuallypackageddiscreteMOSFETsordualMOSFETsinastandardpackage,thein-circuitswitchingperformanceofthesolutionmustbeconsidered.Inthisexample,individuallypackageddiscreteMOSFETsordualMOSFETsinastandardpackagewouldneedtohaveDCmeasuredRDS(ON)valuesthatareequivalenttoCSD87351Q5D’sZDS(ON)valueinordertohavethesameefficiencyperformanceatfullload.Midtolight-loadefficiencywillstillbelowerwithindividuallypackageddiscreteMOSFETsordualMOSFETsinastandardpackage.ComparisonofRDS(ON)vs.EffectiveACOn-ImpedanceZDS(ON)(VGS=--DCMeasuredRDS(ON)(VGS=TheCSD87351Q5DNexFET™powerblockisanoptimizeddesignforsynchronousbuckapplicationsusing5Vgatedrive.TheControlFETandSyncFETsiliconareparametricallytunedtoyieldthelowestpowerlossandhighestsystemefficiency.Asaresult,anewratingmethodisneededwhichistailoredtowardsamoresystemscentricenvironment.SystemlevelperformancecurvessuchasPowerLoss,SafeOperatingArea,andnormalizedgraphsallowengineerstopredicttheproductperformanceintheactualapplication.PowerLossMOSFETcentricparameterssuchasRDS(ON)andQgdareneededtoestimatethelossgeneratedbythedevices.Inanefforttosimplifythedesignprocessforengineers,TexasInstrumentshasprovidedmeasuredpowerlossperformancecurves.Figure1plotsthepowerlossoftheCSD87351Q5Dasafunctionofloadcurrent.ThiscurveismeasuredbyconfiguringandrunningtheCSD87351Q5Dasitwouldbeinthefinalapplication(seeFigure32).ThemeasuredpowerlossistheCSD87351Q5Dlossandconsistsofbothinputconversionlossandgatedriveloss.Equation1isusedtogeneratethepowerlosscurve.(VINxIIN)+(VDDxIDD)–(VSW_AVGxIOUT)=Power ThepowerlosscurveinFigure1ismeasuredatthe mendedjunctiontemperaturesof125°Cunderisothermaltestconditions.SafeOperatingCurvesTheSOAcurvesintheCSD87351Q5Ddatasheetprovidesguidanceonthetemperatureboundarieswithinanoperatingsystembyincorporatingthethermalandsystempowerloss.Figure3toFigure5outlinethetemperatureandairflowconditionsrequiredforagivenloadcurrent.Theareaunderthecurvedictatesthesafeoperatingarea.AllthecurvesarebasedonmeasurementsmadeonaPCBdesignwithdimensionsof4”(W)x3.5”(L)x0.062”(T)and6copperlayersof1oz.copperNormalizedThenormalizedcurvesintheCSD87351Q5DdatasheetprovidesguidanceonthePowerLossandSOAadjustmentsbasedontheirapplicationspecificneeds.ThesecurvesshowhowthepowerlossandSOAboundarieswilladjustforagivensetofsystemsconditions.TheprimaryY-axisisthenormalizedchangeinpowerlossandthesecondaryY-axisisthechangeissystemtemperaturerequiredinordertocomplywiththeSOAcurve.ThechangeinpowerlossisamultiplierforthePowerLosscurveandthechangeintemperatureissubtractedfromtheSOAcurve.Figure32.TypicalCalculatingPowerLossandTheusercanestimateproductlossandSOAboundariesbyarithmeticmeans(seeDesignExample).ThoughthePowerLossandSOAcurvesinthisdatasheetaretakenforaspecificsetoftestconditions,thefollowingprocedurewilloutlinethestepstheusershouldtaketopredictproductperformanceforanysetofsystemDesignOperatingOutputCurrent=InputVoltage=OutputVoltage=SwitchingFrequency=Inductor=CalculatingPowerPowerLossat25A=3.5W(FigureNormalizedPowerLossforinputvoltage≈1.07(FigureNormalizedPowerLossforoutputvoltage≈0.95(FigureNormalizedPowerLossforswitchingfrequency≈1.11(FigureNormalizedPowerLossforoutputinductor≈1.07(FigureFinalcalculatedPowerLoss=3.5Wx1.07x0.95x1.11x1.07≈CalculatingSOASOAadjustmentforinputvoltage≈2ºC(FigureSOAadjustmentforoutputvoltage≈-1.3ºC(FigureSOAadjustmentforswitchingfrequency≈2.8ºC(FigureSOAadjustmentforoutputinductor≈1.6ºC(FigureFinalcalculatedSOAadjustment=2+(-1.3)+2.8+1.6≈Inthedesignexampleabove,theestimatedpowerlossoftheCSD87351Q5Dwouldincreaseto4.23W.Inaddition,the umallowableboardand/orambienttemperaturewouldhavetodecreaseby5.1ºC.Figure33graphicallyshowshowtheSOAcurvewouldbeadjustedaccordingly.StartbydrawingahorizontallinefromtheapplicationcurrenttotheSOADrawaverticallinefromtheSOAcurveinterceptdowntotheboard/ambientAdjusttheSOAboard/ambienttemperaturebysubtractingthetemperatureadjustmentInthedesignexample,theSOAtemperatureadjustmentyieldsareductioninallowableboard/ambienttemperatureof5.1ºC.Intheeventtheadjustmentvalueisanegativenumber,subtractingthenegativenumberwouldyieldanincreaseinallowableboard/ambienttemperature.1V1V=12VV=5VV=13Vf=500kHzL=0.323OutputOutputCurrent Figure33.PowerBlock

MENDEDPCBDESIGNTherearetwokeysystem-levelparametersthatcanbeaddressedwithaproperPCBdesign:ElectricalandThermalperformance.ProperlyoptimizingthePCBlayoutwillyield umperformanceinbothareas.Abriefdescriptiononhowtoaddresseachparameterisprovided.ElectricalThePowerBlockhastheabilitytoswitchvoltagesatratesgreaterthan10kV/µs.SpecialcaremustbethentakenwiththePCBlayoutdesignandcementoftheinputcapacitors,DriverIC,andoutputinductor.ThecementoftheinputcapacitorsrelativetothePowerBlock’sVINandPGNDpinsshouldhavethehighestpriorityduringthecomponentcementroutine.Itiscriticaltominimizethesenodelengths.Assuch,ceramicinputcapacitorsneedtobecedascloseaspossibletotheVINandPGNDpins(seeFigure34).TheexampleinFigure34uses6x10µFceramiccapacitors(TDKPart#C3216X5R1C106KTorequivalent).Noticethereareceramiccapacitorsonbothsidesoftheboardwithanappropriateamountofviasinterconnectingbothlayers.IntermsofpriorityofcementnexttothePowerBlock,C5,C7,C19,andC8shouldfollowinorder.TheDriverICshouldbecedrelativelyclosetothePowerBlockGatepins.TGandBGshouldconnecttotheoutputsoftheDriverIC.TheTGRpinservesasthereturnpathofthehigh-sidegatedrivecircuitryandshouldbeconnectedtothePhasepinoftheIC(sometimescalledLX,LL,SW,PH,etc.).ThebootstrapcapacitorfortheDriverICwillalsoconnecttothispin.TheswitchingnodeoftheoutputinductorshouldbecedrelativelyclosetothePowerBlockVSWpins.MinimizingthenodelengthbetweenthesetwocomponentswillreducethePCBconductionlossesandactuallyreducetheswitchingnoiselevel.TheswitchingnodeoftheoutputinductorshouldbecedrelativelyclosetothePowerBlockVSWpins.MinimizingthenodelengthbetweenthesetwocomponentswillreducethePCBconductionlossesandactuallyreducetheswitchingnoiselevel.Intheeventtheswitchnodewaveformexhibitsringingthatreachesundesirablelevels,theuseofaBoostResistororRCsnubbercanbeaneffectivewaytoreducethepeakringlevel.The mendedBoostResistorvaluewillrangebetween1Ωto4.7ΩdependingontheoutputcharacteristicsofDriverICusedinconjunctionwiththePowerBlock.TheRCsnubbervaluescanrangefrom0.5Ωto2.2ΩfortheRand330pFto2200pFfortheC.RefertoTIAppNoteSLUP100formoredetailsonhowtoproperlytunetheRCsnubbervalues.TheRCsnubbershouldbecedascloseaspossibletotheVswnodeandPGNDseeFigure34(1)KeongW.Kam,DavidPommerenke,“EMIysisMethodsforSynchronousBuckConverterEMIRootCauseysis”,UniversityofMissouri–RollaThermalThePowerBlockhastheabilitytoutilizetheGNDnesastheprimarythermalpath.Assuch,theuseofthermalviasisaneffectivewaytopullawayheatfromthedeviceandintothesystemboard.Concernsofsoldervoidsandmanufacturabilityproblemscanbeaddressedbytheuseofthreebasictacticstominimizetheamountofsolderattachthatwillwickdowntheviabarrel:IntentionallyspaceouttheviasfromeachothertoavoidaclusterofholesinagivenUsethesmallestdrillsizeallowedinyourdesign.TheexampleinFigure34usesviaswitha10mildrillholeanda16milcapturepad.Tenttheoppositesideoftheviawithsolder-Intheend,thenumberanddrillsizeofthethermalviasshouldalignwiththeenduser’sPCBdesignrulesandmanufacturingcapabilities.Figure mendedPCBLayout(TopDownMECHANICALKLLKLLb9def45 45 236 236cFront

SideExposedTieBarMaya

PinPinPinPinPinPinPinPinPin

abcdEe1.27fLθ–––KLand 540540NOTE:Dimensionsareinmm

8181

54 54 8181 NOTE:Dimensionsareinmm

mendedcircuitlayoutforPCBdesigns,seeapplicationnoteSLPA005–ReducingRingingThroughPCBLayoutTechniques.Q5DTapeandReel

4.00±0.10(SeeNote

ØØ Ø1.50 R0.30NOTES:1.10- hole-pitchcumulativetolerance

A0=5.30B0=6.50K0=1.90

Cambernottoexceed1mmin100mm,noncumulativeoverMaterial:blackstatic-dissipativeAlldimensionsareinmm,unlessotherwiseThickness:0.30MSL1260°C(IRandconvection)PbFreflowREVISIONChangesfromOriginal(March2011)toRevision RecedRDS(on)with AddedEquivalentSystemPerformance ChangesfromRevisionA(August2011)toRevision Remove Remove AddedElectricalPerformance ChangesfromRevisionB(September2011)toRevision Changed"DIMa"MillimeterMaxvalueFrom:1.55To:1.5andInchesMaxvalueFrom:0.061To: ChangesfromRevisionC(October2011)toRevision PACKAGEOPTIONPACKAGINGOrderableStatusPackagePackageEconMSLPeak8CU(1)ThemarketingstatusvaluesaredefinedasACTIVE:Product mendedfornewLIFEBUY:TIhasannouncedthatthedevicewillbedis,andalifetime-buyperiodisin mendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoes mendusingthispartinanewPREVIEW:Devicehasbeenannouncedbutisnotinproduction.SamplesmayormaynotbeOBSOLETE:TIhasdistheproductionofthe(2)Eco n-Thennedeco-friendlyclassification:Pb- (RoHS),Pb- (RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck informationandadditionalproductcontentdetails.TBD:ThePb-/Green nhasnotbeenPb-(RoHS):TI'sterms"Lead- "or"Pb- "meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb- productsaresuitableforuseinspecifiedlead-processes.Pb-(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)le