单片机【经典外文翻译】-max-ii-cpld系列概述及应用(英文+译文)--毕业论文设计

MAXIICPLD:LowestPower,LowestCostCPLDFamilyEverAltera'sMAX®IIfamilyofCPLDfamilyarethelowestpower,lowestcostCPLDsever.MAXIICPLDfamilyisbasedonagroundbreakingarchitecturethatdeliversthelowestpowerandthelowestcostperI/OpinofanyCPLDfamily.WiththeintroductionoftheMAXIIZCPLD,therearenowthreevariantsthatallusethesameinnovativeCPLDarchitecture:MAXIICPLDMAXIIGCPLDMAXIIZCPLDThisinstant-on,non-volatileCPLDfamilytargetsgeneral-purpose,low-densitylogicand

portableapplications,suchascellularhandsetdesign.InadditiontodeliveringthelowestcostfortraditionalCPLDdesigns,theMAXIICPLDdrivespowerandcostimprovementstohigherdensities,enablingyoutouseaMAXIICPLDinplaceofahigherpowerorhighercostASSPorandstandard-logicCPLD.AdvancedCPLDfeaturesTheMAXIICPLDenablesahighleveloffunctionalintegrationtoreducesystemdesigncosts.ThissectiondescribestheadvancedfeaturesfoundineveryMAXIICPLD.LowpowerCPLDOne-tenththepowerconsumption(comparedto

aprevious-generation3.3-V

MAXCPLD)1.8-VcorevoltageforreducedpowerconsumptionandincreasedreliabilityCPLDindustry'sloweststandbyspecification,allowinglongeruse

inbatterypoweredapplicationsAutostart/stopcapabilityforturningofftheCPLDwhennotinuseCost-optimizedarchitectureFourtimesthedensityathalftheprice(comparedtopreviousMAX

CPLDgenerations)Designed

forminimumdiesize,givingthelowestcostperI/OpinintheindustryHighperformanceSupportforinternalclockfrequencyratesofupto300MHzTwice

theperformance(comparedtoa3.3-VMAXCPLD)UniquefeaturesOn-boardoscillator

anduser

flash

memoryReduceschipcountbyeliminatingdiscreteoscillatorsor

non-volatilestoragedevicesReal-timein-systemprogrammability(ISP)CapableofdownloadingaseconddesignwhilethedeviceisoperationalReducesthecostofremotefieldupdatesMultiVoltcoreflexibilityOn-chipvoltageregulatoraccepts3.3-V,2.5-V,or1.8-VsupplySimplifiesboarddesignwithfewerpowerrailsParallelflashloadermegafunctionImprovesconfigurationefficiencyofnon-JTAG-compliantflashdevicesontheboardSimplifiesboardmanagementbyallowingJTAGcommandimplementationviatheMAXII

CPLDI/OcapabilitiesMultiVoltI/Ocapabilityallowsinterfacewithdevicesat1.5-V,1.8-V,2.5-V,or3.3-VlogiclevelsSchmitttriggers,programmableslewrate,and

programmabledrivestrengthimprovesignalintegrityEasiest-to-usesoftwareAltera’sno-costQuartus®

IIWebEditionsoftwaresupportsalldevicesintheMAXIICPLDfamily

and

optimizespin-lockedfitting

andperformanceNewMAX+PLUS®

IIlook-and-feeloptionintheQuartusIIsoftwareenhanceseaseofuseCPLDApplicationsTheMAXIICPLDfamilytargetscommoncontrolpathapplications,including:Power-upsequencingSystemconfigurationI/OexpansionInterfacebridging

MAXIICPLD系列概述及应用

Altera的MAX®II系列CPLD是有史以来功耗最低、成本最低的CPLD。MAXIICPLD基于突破性的体系结构，在所有CPLD系列中，其单位I/O引脚的功耗和成本都是最低的。随着MAXIIZ的推出，有三种型号产品都使用了同样的创新CPLD体系结构：MAXIICPLDMAXIIGCPLDMAXIIZCPLD这一瞬时接通的非易失器件系列面向蜂窝手机设计等通用低密度逻辑应用。不但具有传统CPLD设计的低成本特性，MAXIICPLD还进一步提高了高密度产品的功耗和成本优势，这样，您可以使用MAXIICPLD来替代高功耗和高成本ASSP以及标准逻辑CPLD。

MAXII器件系列的高级特性MAXIICPLD支持高级功能集成，以降低系统设计成本。这一部分介绍MAXIICPLD的高级特性。低功耗

十分之一的功耗(和前一代3.3VMAX器件相比)1.8V内核电压降低了功耗，提高可靠性。CPLD业界最低的待机规范，大大延长了电池供电时间。自动启动/停止功能，CPLD不使用时关断。低成本体系结构

以一半的价格实现四倍的密度(和前一代MAX器件相比)通过设计，减小了管芯面积，单位I/O引脚成本在业界是最低的。高性能

支持高达300MHz的内部时钟频率性能加倍(和3.3-VMAX器件相比)独特的特性

板上振荡器和用户闪存不需要分立振荡器或者非易失存储器，减少了芯片数量。实时在系统可编程能力(ISP)器件工作时，可下载第二个设计。降低了远程现场更新的成本灵活的MultiVolt内核片内电压稳压器支持3.3-V、2.5-V和1.8-V供电减少了电源数量，简化了电路板设计。并行闪存加载程序宏功能

提高了板上不兼容JTAG闪存的配置效率通过MAXII器件实现JTAG命令，简化了电路板管理。I/O能力

MultiVoltI/O支持和1.5-V、1.8-V、2.5-V以及3.3-V逻辑电平器件的接口施密特触发器、可编程摆率和可编程驱