外文翻译-数字频率合成器

附录2：外文原文，译文ModulatingDirectDigitalSynthesizerInthepursuitofmorecomplexphasecontinuousmodulationtechniques,thecontroloftheoutputwaveformbecomesincreasinglymoredifficultwithanalogcircuitry.Inthesedesigns,usinganon-lineardigitaldesigneliminatestheneedforcircuitboardadjustmentsoveryieldandtemperature.AdigitaldesignthatmeetsthesegoalsisaDirectDigitalSynthesizerDDS.ADDSsystemsimplytakesaconstantreferenceclockinputanddividesitdownatoaspecifiedoutputfrequencydigitallyquantizedorsampledatthereferenceclockfrequency.ThisformoffrequencycontrolmakesDDSsystemsidealforsystemsthatrequireprecisefrequencysweepssuchasradarchirpsorfastfrequencyhoppers.Withcontrolofthefrequencyoutputderivedfromthedigitalinputword,DDSsystemscanbeusedasaPLLallowingprecisefrequencychangesphasecontinuously.Aswillbeshown,DDSsystemscanalsobedesignedtocontrolthephaseoftheoutputcarrierusingadigitalphasewordinput.Withdigitalcontroloverthecarrierphase,ahighspectraldensityphasemodulatedcarriercaneasilybegenerated.ThisarticleisintendedtogivethereaderabasicunderstandingofaDDSdesign,andanunderstandingofthespuriousoutputresponse.Thisarticlewillalsopresentasampledesignrunningat45MHzinahighspeedfieldprogrammablegatearrayfromQuickLogic.AbasicDDSsystemconsistsofanumericallycontrolledoscillator(NCO)usedtogeneratetheoutputcarrierwave,andadigitaltoanalogconverter(DAC)usedtotakethedigitalsinusoidalwordfromtheNCOandgenerateasampledanalogcarrier.SincetheDACoutputissampledatthereferenceclockfrequency,awaveformsmoothinglowpassfilteristypicallyusedtoeliminatealiascomponents.Figure1isabasicblockdiagramofatypicalDDSsystemdesign.ThegenerationoftheoutputcarrierfromthereferencesampleclockinputisperformedbytheNCO.ThebasiccomponentsoftheNCOareaphaseaccumulatorandasinusoidalROMlookuptable.AnoptionalphasemodulatorcanalsobeincludeintheNCOdesign.ThisphasemodulatorwilladdphaseoffsettotheoutputofthephaseaccumulatorjustbeforetheROMlookuptable.ThiswillenhancetheDDSsystemdesignbyaddingthecapabilitiestophasemodulatethecarrieroutputoftheNCO.Figure2isadetailedblockdiagramofatypicalNCOdesignshowingtheoptionalphasemodulator.FIGURE1:TypicalDDSSystem.FIGURE2:TypicalNCODesign.TobetterunderstandthefunctionsoftheNCOdesign,firstconsiderthebasicNCOdesignwhichincludesonlyaphaseaccumulatorandasinusoidalROMlookuptable.ThefunctionofthesetwoblocksoftheNCOdesignarebestunderstoodwhencomparedtothegraphicalrepresentationofEuler’sformulaejwt=cos(wt)+jsin(wt).ThegraphicalrepresentationofEuler’sformula,asshowninFigure3,isaunitvectorrotatingaroundthecenteraxisoftherealandimaginaryplaneatavelocityofwrad/s.Plottingtheimaginarycomponentversustimeprojectsasinewavewhileplottingtherealcomponentversustimeprojectsacosinewave.ThephaseaccumulatoroftheNCOisanalogous,orcouldbeconsidered,thegeneratoroftheangularvelocitycomponentwrad/s.Thephaseaccumulatorisloaded,synchronoustothereferencesampleclock,withanNbitfrequencyword.ThisfrequencywordiscontinuouslyaccumulatedwiththelastsampledphasevaluebyanNbitadder.TheoutputoftheadderissampledatthereferencesampleclockbyanNbitregister.WhentheaccumulatorreachestheNbitmaximumvalue,theaccumulatorrollsoverandcontinues.PlottingthesampledaccumulatorvaluesversustimeproducesasawtoothwaveformasshownbelowinFigure3.FIGURE3Euler’sEquationRepresentedGraphicallyThesampledoutputofthephaseaccumulatoristhenusedtoaddressaROMlookuptableofsinusoidalmagnitudevalues.Thisconversionofthesampledphasetoasinusoidalmagnitudeisanalogoustotheprojectionoftherealorimaginarycomponentintime.Sincethenumberofbitsusedbythephaseaccumulatordeterminesthegranularityofthefrequencyadjustmentsteps,atypicalphaseaccumulatorsizeis24to32bits.SincethesizeofthesinusoidalROMtableisdirectlyproportionaltotheaddressingrange,notall24or32bitsofthephaseaccumulatorareusedtoaddresstheROMsinusoidaltable.OnlytheupperYbitsofthephaseaccumulatorareusedtoaddressthesinusoidalROMtable,whereY<NbitsandYistypicallybutnotnecessarilyequaltoD,andDisthenumberofoutputmagnitudebitsfromthesinusoidalROMtable.SinceanNCOoutputsacarrierbasedonadigitalrepresentationofthephaseandmagnitudeofthesinusoidalwaveform,designershavecompletecontroloverfrequency,phase,andevenamplitudeoftheoutputcarrier.ByaddingaphaseportandaphaseaddertothebasicNCOdesign,theoutputcarrieroftheNCOcanbeMarrayphasemodulatedwhereMequalsthenumberofphaseportbitsandwhereMislessthanorequaltotheYnumberofbitsusedtoaddressthesinusoidalROMtable.ForsystemdesignsthatrequireamplitudemodulationsuchasQAM,amagnitudeportcanbeaddedtoadjustthesinusoidalROMtableoutput.NotethatthisportisnotshowninFigure2andthatthisfeatureisnotdemonstratedinthesampleQuickLogicFPGAdesign.Finally,frequencymodulationisagivenwiththebasicNCOdesign.Thefrequencyportcandirectlyadjustthecarrieroutputfrequency.SincefrequencywordsareloadedintotheDDSsynchronoustothesampleclock,frequencychangesarephasecontinuous.AlthoughDDSsystemsgivethedesignercompletecontrolofcomplexmodulationsynthesis,therepresentationofsinusoidalphaseandmagnitudeinanon-lineardigitalformatintroducesnewdesigncomplexities.Insamplinganycontinuous-timesignal,onemustconsiderthesamplingtheoryandquantizationerror.TounderstandtheeffectsofthesamplingtheoryonaDDSsystem,itisbesttolookattheDDSsynthesisprocessesinboththetimeandfrequencydomain.Asstatedabove,theNCOgeneratesasinusoidalwaveformbyaccumulatingthephaseataspecifiedrateandthenusesthephasevaluetoaddressaROMtableofsinusoidalamplitudevalues.Thus,theNCOisessentiallytakingasinusoidalwaveformandsamplingitwiththerisingorfallingedgeoftheNCOinputreferencesamplingclock.Figure4showsthetimeandfrequencydomainoftheNCOprocessing.Notethatthisrepresentationdoesnotassumequantization.Basedontheloadedfrequencyword,theNCOproducesasetofamplitudeoutputvaluesatasetperiod.Thefrequencydomainrepresentationofthissinusoidisanimpulsefunctionatthespecifiedfrequency.TheNCO,however,outputsdiscretedigitalsamplesofthissinusoidattheNCOreferenceclockrate.Inthetimedomain,theNCOoutputisafunctionofthesamplingclockedgestrobesmultipliedbythesinusoidwaveformproducingatrainofimpulsesatthesinusoidamplitude.Inthefrequencydomain,thesamplingstrobesofthereferenceclockproduceatrainofimpulsesatfrequenciesofKtimestheNCOclockfrequencywhereK=...-1,0,1,2....Sincethesamplingclockwasmultipliedbythesinusoidinthetimedomain,thefrequencydomaincomponentsofthesinusoidandthesamplingclockneedtobeconvolvedtoproducethefrequencydomainrepresentationoftheNCOoutput.ThefrequencydomainresultsaretheimpulsefunctionatthefundamentalfrequencyofthesinusoidandthealiasimpulsefunctionsoccurringatKtimestheNCOclockfrequencyplusorminusthefundamentalfrequency.Thefundamentalandaliascomponentoccurat:K*Fclk-FoutK*Fclk+FoutWhereK=...-1,0,1,2.....andK=0istheNCOsinusoidfundamentalfrequencyFoutisthespecifiedNCOsinusoidoutputfrequencyFclkistheNCOreferenceclockfrequencyFIGURE4NCOOutputRepresentationTimeandFrequencyDomainTheDACoftheDDSsystemtakestheNCOoutputvaluesandtranslatesthesevaluesintoanalogvoltages.Figure4showsthetimeandfrequencydomainrepresentationsoftheDACprocessingstartingwiththeNCOoutput.TheDACoutputisasampleandholdcircuitthattakestheNCOdigitalamplitudewordsandconvertsthevalueintoananalogvoltageandholdsthevalueforonesampleclockperiod.ThetimedomainplotoftheDACprocessingistheconvolutionoftheNCOsampledoutputvalueswithapulseofonesampleclockperiod.Thefrequencydomainplotofthesamplingpulseisasin(x)/xfunctionwiththefirstnullatthesampleclockfrequency.Sincethetimedomainwasconvolved,thefrequencydomainismultiplied.ThismultiplicationdampenstheNCOoutputwiththesin(x)/xenvelope.ThisattenuationattheDACoutputcanbecalculatedasfollowsandasampleoutputspectrumisshowninFigure5:Atten(F)=20log[(sin(pF/Fclk)/pF/Fclk)]WhereFistheoutputfrequencyFclkisthesampleclockfrequencyFIGURE5:DACOutputRepresentationinTimeandFrequencyDomainAsidefromthesamplingtheory,thequantizationoftherealvaluesintodigitalformmustalsobeconsideredintheperformanceanalysisofaDDSsystem.ThespuriousresponseofaDDSsystemisprimarilydictatedbytwoquantizationparameters.TheseparametersarethephasequantizationbythephaseaccumulatorandthemagnitudequantizationbytheROMsinusoidaltableandtheDAC.Asmentionedabove,onlytheupperYbitsofthephaseaccumulatorareusedtoaddresstheROMlookuptable.Itshouldbenoted,however,thatusingonlytheupperYbitsofthephaseaccumulatorintroducesaphasetruncation.Whenafrequencywordcontaininganon-zerovalueinthelower(N-Y-1:0)bitsisloadedintotheDDSsystem,thelowernon-zerobitswillaccumulatetotheupperYbitsandcauseaphasetruncation.Thefrequencyatwhichthephasetruncationoccurscanbecalculatedbythefollowing:Ftrunc=FW(N-Y-1:0)/2N-Y*Fclk.Aphasetruncationwillperiodically(attheFtruncrate)phasemodulatetheoutputcarrierforward2p/28tocompensateforfrequencywordgranularitygreaterthan2Y.Thephasejumpcausedbytheaccumulationofphasetruncatedbitsproducesspursaroundthefundamental.Thesespursarelocatedplusandminusthetruncationfrequencyfromthefundamentalfrequencyandthemagnitudeofthespurswillbe-20log(2Y)dBc.AsampleoutputofaphasetruncationspurisshowninFigure5.InatypicalNCOdesign,theROMsinusoidaltablewillholda¼sinewave(0,p/2)ofmagnitudevalues.TheROMtableisgeneratedbytakingallpossiblephasevalueaddressesandmaptoarealmagnitudesinevalueroundedtothenearestDbits.Thus,themaximumerroroutputis±-½LSBgivingaworstcasespurof-20log(2D)dBc.LiketheNCOROMtable,aDACquantizesthedigitalmagnitudevalues.ADAC,however,outputsananalogvoltagecorrespondingtothedigitalinputvalue.WhendesigningtheNCOsinusoidalROMtable,oneshouldtakesomeempiricaldataontheDAClinearitytobetterunderstandtheinteractionbetweentheROMtableandtheDAC.ThequantizationforaDACisspecifiedagainstanideallinearplotofdigitalinputversusanalogoutput.Twolinearityparameters,differentialandintegrallinearity,areusedtospecifyaDAC’sperformance.Differentiallinearityistheoutputstepsizefrombittobit.ADACmustguaranteeadifferentiallinearityofamaximum1LSB.Whenaninputcodeisincreased,theDACoutputmustincrease.IftheDACvoltagedoesnotincreaseversusanincreasedigitalinputvalue,theDACissaidtobemissingcodes.Thus,a10bitDACthathasadifferentiallinearityofgreaterthat1LSBisonlyaccurateto9orlessbits.ThenumberofaccurateoutputbitswillspecifytheDDSspuriousperformanceas-20log(2dl)wheredlisthenumberdifferentiallinearbits..IntegrallinearityisameasureoftheDAC’soveralllinearperformanceversusanideallinearstraightline.Thestraightlineplotcanbeeithera“beststraightline”whereDCoffsetsarepossibleatboththeminandmaxoutputsoftheDAC,orthestraightlinecancrosstheendpointsoftheminandmaxoutputvalues.ADACwilltendtohaveacharacteristiccurvethatistraversedovertheoutputrange.Dependingontheshapeandsymmetry(symmetryaboutthehalfwaypointoftheDACoutput)ofthiscurve,outputharmonicsoftheDDSfundamentaloutputfrequencywillbeproduced.AstheseharmonicsapproachandcrosstheNyquistfrequencyofFclk/2,theharmonicsbecomeundersampledandreflectbackintothebandofinterest,0toFclk/2.ThisproblemisbestillustratedbysettingtheNCOoutputtoFclk/4plusaslightoffset.Thethirdharmonicwillfallminus3foldsthesmalloffsetfromthefundamentalandthesecondharmonicwillcrosstheNyquistfrequencyby2foldsthesmalloffsetleavingareflectedimagebackinthebandofinterestAsampleplotofthisfrequencysetupisshowninFigure5.OtherDACcharacteristicthatwillproduceharmonicdistortionisanydisruptionofthesymmetryoftheoutputwaveformsuchasadifferentriseandfalltime.ThesecharacteristicscantypicallybecorrectedbyboardcomponentsexternaltotheDACsuchasanRFtransformer,boardlayoutissues,attenuationpadsetc.GiventhecomplexitiesoftheDDSsystem,engineersshouldconsiderimplementingthedesignusingseparatedevicesforthenumericallycontrolledoscillator,thedigitaltoanalogconverter,andthelowpassfilter.Thisapproachallowsforsignalobservationatmanypointsinthesystem,yetiscompactenoughtobepracticalasanend-solution.Alternatively,thediscreteimplementationcanserveasaprototypingvehicleforasingle-chipmixedsignalASIC.TheauthordevelopedaversionofthedesignusingaHarrisHI5721evaluationboardfortheDAC.TheNCOattheheartoftheDDSdesign,andarandomgeneratortotestsignalmodulation,wasimplementedintoabout65%ofaQuickLogicfieldprogrammablegatearray(FPGA).ThisFPGA,aQL16x24B4000-gatedevice,waschosenforitshighperformance,ease-of-use,andpowerfuldevelopmenttools.TheNCOdesignincludedfollowing:DevelopedinVerilogwiththe8bitCLAadderschematiccapturedandnetlistedtoVerilog32bitfrequencywordinput32phaseaccumulatorpipelinedover8bits8bitphasemoudulationwordinput8bitsineROMlook-uptableThedesignwasdescribedmostlyinVerilog,withan8bitcarrylookaheadaddermodifiedfromQuickLogic’smacrolibrarynetlistedtoVerilog.Thewholedesigncyclewaslessthanfourdays(twodaystodescribethedesignandadayandahalftoprototypethehardware).Everythingworkedperfectlythefirsttime,withthedesignrunningatanimpressive45MHzaspredictedbythesoftwaresimulationtools.PlotsusedinthearticletoillustrateDDSperformanceparameterswereprovidedfromthetestconfiguration.Figure6belowshowstheexternalIOinterfacetotheNCOdesign.Thefunctionofeachsignalisdescribedinthefollowingtable.SignalFunctionTableFREQWORD[31:0]ThisinputisthefrequencycontrolwordtotheNCO.Thiswordcontrolsthephaseaccumulatorrate,andthus,theoutputfrequencyoftheDACOUTsinusoidalwaveform.Theoutputcarrierfrequencyiscalculatedbythefollowing:PHASEWORD[7:0]ThisinputisthephasemodulationcontrolwordtotheNCO.Thiswordcontrolsthephaseoffsetfollowingthephaseaccumulator.Thisphaseoffsetisusedtophasemodulatetheoutputcarrier.FWWRNThisinputisthelowassertedfrequencywordwritestrobe.ThisstrobeinputregisterstheFREQWORDinputontherisingedge.ThisstrobecanbeasynchronoustotheSYSCLK.SYSCLKThisisthereferencesystemclockinputtotheNCO.Thisclockisthesamplingclockoftheoutputcarrier.PNCLKThisinputisthepseudo-noisegeneratorclockinput.ThisclocksetsthedatarateoftheIandQdataoutputs.RESETNThisinputisalowassertedglobalreset.Whenasserted,theinternalphaseandfrequencywordregistersareclearedstoppingtheoutputcarrierat0radians.DACOUT[7:0]ThisoutputisthesinusoidalDACamplitudeword.ThiswordisvalidontherisingedgeoftheDACCLK.Thesinusoidalwaveformoutputisrepresentedbythefollowing:f(t)=sin(2pFout(t)+Pout)DACCLKThisoutputistheDACclockstrobe.ThisclockistheSYSCLKfeedbacktoanoutputpincompensatingforthelatencyoftheNCOIOpins.TheDACOUTamplitudewordswillbevalidontherisingedgeoftheDACCLK.SINThisoutputisasinglebitdigitalsinewaveoutput.ThissinewaveoutputcomesfromtheMSBofthephaseaccumulator.Theoutputfrequencyofthispiniscontrolledbythefrequencywordinput.COSThisoutputisasinglebitdigitalcosinewaveoutput.ThiscosinewaveoutputcomesformtheMSBandnextmostsignificantbitofthephaseaccumulator.Theoutputfrequencyofthispiniscontrolledbythefrequencywordinput.MSINThisoutputisasinglebitdigitalsinewaveoutput.ThissinewaveoutputcomesfromtheMSBofthephasemodulator.Theoutputfrequencyofthispiniscontrolledbythefrequencywordinputandphaseoffsetbythephasewordinput.ThissinewaveoutputisthesameastheSINoutputwithaphaseoffsetofplus2p/28*PHASEWORD.MCOSThisoutputisasinglebitdigitalcosinewaveoutput.ThiscosinewaveoutputcomesformtheMSBandnextmostsignificantbitofthephasemodulator.Theoutputfrequencyofthispiniscontrolledbythefrequencywordinputandthephaseoffsetbythephasewordinput.ThiscosinewaveoutputisthesameastheCOSoutputwithaphaseoffsetofplus2p/28*PHASEWORD.IDATAThisoutputisa25-1pseudonoiserandompattern.ThisoutputisnotafunctionalpartoftheNCOdesignbutusedtodemonstratephasemodulationusingthephaseport.QDATAThisoutputisa25-1pseudonoiserandompattern.ThisoutputisnotafunctionalpartoftheNCOdesignbutusedtodemonstratephasemodulationusingthephaseport.Figure6:TheExternalIOInterfaceTopLevel(dds.v)ThetopleveloftheNCOdesigninstantiatesthefunctionalblocksoftheNCOdesignandthePNgeneratorblock.PNGenerator(pngen.v)ThismoduleisnotpartoftheNCOdesignbutisusedtoproduceasamplerandomdatapatterntomodulatethecarrieroutput.ThismoduleusesthePNCLKinputtoclocktwoGoldcode5bitPNgenerators.TheoutputsofthePNgeneratorsareIDATAandQDATAoutputs.ThelowerlevelblockofthisNCOdesignconsistofasynchronousfrequencywordinputregister,asynchronousphasewordinputregister,a32bitpipelinedphaseaccumulator,an8bitphaseadder,andasinlockuptable.AdetaileddescriptionofeachoftheNCOblocksandthePNgeneratorareprovidedinthefollowingsections.LoadFrequencyWord(loadfw.v)Theloadfrequencywordblockisasynchronizingloadingcircuit.TheFREQWORD[31:0]inputdrivesathedatainputtothe32bitfwregregisterthatissampledontherisingedgeoftheFWWRNwritestrobe.TheFWWRNstrobealsodrivesthedatainputtoametastableflipflopfwwrnmthatisusedinconjunctionwithasynchronousregisterfwwrnstoproduceaFWWRNrisingedgestrobe.Thisrisingedgestrobeloadp1isthenpipedforanadditional3clockcyclesproducingtheloadstrobesloadp2,loadp3,andloadp4.Theloadstrobesareusedtosignalwhentoupdatethesynchronouspipeline8bitregisterspipefw1,pipefw2,pipefw3,andpipefw4tothesampledfrequencywordcontent.Thepipelineregistersareconcatenatedtoproducethe32bitsynchronousfrequencywordoutputSYNCFREQ[31:0]thatisstaggeredtocompensateforthe32bitpipelinedphaseadder.PhaseWordAccumulator(phasea.v)Thephaseaccumulatorblockisa32bitaccumulatorthatispipelinedin8bitsections.ThismoduleinstanciatesaschematiccapturedcarrylockaheadCLAadderthathasacarryinandcarryoutport.Thesynchronousfrequencyword,staggeredtomatchthepipelinedaccumulator,isloadedintotheBinputoftheCLAadders.ThesumoutputoftheCLAaddersareregisteredinthepiperegisteredwiththeoutputtiedbacktotheAinputoftheCLAadders.ThecarryoutputoftheCLAaddersisregisteredinthepipecregisterswiththeoutputtiedtothenextmostsignificantCLAaddercarryinput.Themostsignificantsumoutputregisterpipe4isassignedtothePHASEoutputportgivingaphasevaluequantizedto8bits.Adigitalsineandcosinevalueisalsocalculatedfromthepipe4registerandbroughtoutofthechipasSINandCOS.LoadPhaseWord(loadpw.v)Theloadphasewordblockisasynchronizingloadingcircuit.ThePHASEWORD[7:0]inputdrivesthedatainputtothe32bitpwregregisterthatissampledontherisingedgeofthePWWRNwritestrobe.ThePWWRNstrobealsodrivesthedatainputtoametastableflipfloppwwrnmthatisusedinconjunctionwithasynchronousregisterpwwrnstoproduceaFWWRNrisingedgestrobe.Thisrisingedgestrobeloadisusedtosignalwhentoupdatethesynchronousphasewordregisterphswd.ThephswdregisterisassignedtothesynchronousphasewordoutputSYNCPHSWD[7:0].PhaseModulator(phasemod.v)Thephasemodulatorblockisusedtophaseoffsetthephaseaccumulator8bitquantizedoutputwiththesynchronousphasewordfromtheloadphasewordblock.ThismoduleinstantiatesaCLAadderwiththeAinputtiedtothesynchronousphaseoutputandtheBinputtiedtothephaseaccumulatoroutput.ThesumoutputoftheadderisregisteredinthemphsregregisterandassignedtotheMODPHASEoutputport.AmodulatedversionofthesineandcosinevaluesarecalculatedandbroughtoutofthechipasMSINandMCOS.SineLockup(sinlup.v)Thismoduletakesthemodulatedphasevalueformthephasemodulatorblockandtranslatedthequantized8bitvalueintoasinewaveformamplitudevaluequantizedto8bits.ThetranslationfromphasetoamplitudeisperformedbyasineROMtablethatininstantiatedinthismodule.TheROMtableisreducedtoa¼ofthesymmetricalsinewaveformandtheMSBofthesinewaveformisequivalenttothemodulatedphaseinput.Thismoduleperformsthecalculationstoreconstructacompleteperiodofthesinewaveformfromthe¼representationoftheROMtableandtheMSBofthemodulatedphaseinput.Tobetterunderstandtheprocessingofthismodule,considerthefollowing.Themodulatedphasevalueisa0to2pvaluequantizedto8bits2p/28.Thequantizedvalueforp/2,p,3p/2,and2pare0x3F,0x7F,0xBF,and0xFF.Theamplitudevaluesfor0top/2isstoredintheROMtable.Theamplitudevaluesforp/2toparetheROMtableoutputinthereverseorder.Theamplitudevaluesforpto3p/2arethesameoutputastheamplitudevaluefrom0top/2withtheoutputfromtheROMtableinverted.Finallytheamplitudevaluefor3p/2to2parethesameasforpto3p/2withtheROMtableaccessedinreverse.ThismodulemanagestheaddressvaluestotheROMtableandtheamplitudeoutputstoformthecompleteperiodofthesinewaveform.ThefirstprocessofgeneratingthesinewavefunctionistheaddressingoftheROMtablesuchthatphaseanglesp/2topand3p/2to2pareaddressedinthereverseorder.ReverseaddressingisaccomplishedbysimplyinvertingtheROMtableaddressinputvector.ThephasemodulatedaddressinputisinvertedwhentheMODPHASE[6]isoneandisthenregisteredinthephaseaddregister.ThephaseaddressisusedtoaddresstheROMsinetablewiththeoutputregisteredintheqwavesin_ffregister.Toconstructthenegativeamplitudevaluesofthesinewaveform,theMSBofthemodulatephasewordinputisregisteredtwiceinmodphase_msb1_ffandmodphase_msb2_ff,compensatingforthetwocyclelatencyofthephaseaddandqwavesin_ffregisters.ThedelayedMSBbitisusedtoinverttheROMtableoutputwhenone.ThealteredROMtableoutputandtheinvertofthedelayedmodulatedphasewordMSBarefinallyregisteredinbythedac_ffregisterandthenassignedtotheDACOUToutputport.SineROMTable(romtab.v)ThismoduleisthesinewaveformROMtable.Thistableconvertsthephasewordinputtoasineamplitudeoutput.Toconservearea,only¼ofthesymmetricalsinewaveformisstoredintheROM.Thesinevaluesstoredinthistablearethe0top/2unsignedvaluesquantizedto8bits.Thus,theROMtablerequiresa6bitphaseaddressinputandoutputsa7bitamplitudeoutput.Thesinlupmoduleprocessesthephaseandamplitudevaluestoproduceacompletesineperiod.DanMorellihasover9yearsofdesignandmanagementexperience.Hisareasofexpertiseincludespreadspectrumcommunications(involvingGPS,TDRSS,and802.11),PCchipsetandsystemarchitecture,celllibrarydevelopment(forECLdevices)andASICdevelopment.Hehasbeenpublishedandhasmultiplepatentsawardedandpending.DancurrentlyworksforAccelentSystemsInc.,anelectronicdesignconsultingcompany,whereheisafounderandtheVPofEngineering.

数字频率合成器在探讨许多复杂的相位连续的调制技术中，对模拟电路中输出波形的控制已经越来越困难。在这些设计中，使用非线性数字式设计除去电路板需要的调整额外输出和温度。一个适合这个目标的数字式设计就是直接数字频率合成器（DDS）。一个DDS系统仅仅使用一个恒定参考时钟输入和将该时钟分解为指定的量化数位频率输出或者对参考时钟频率取样。这种形式是频率控制使得DDS系统成为需要精确频率扫描比如雷达尖叫声或者快速频率计量器的理想系统。根据数字输入控制字以控制输出频率，DDS系统可以用来当作一个允许精确频率连续改变相位的锁相环（PLL）。根据后面的说明，我们知道DDS系统还可以使用输入数字相位控制字来控制输出载波的相位。用数字式控制载波相位，很容易产生一个高频谱密度的相位调制载波。本文主旨是给读者一个基本的DDS设计和寄生输出响应的知识。本文将展示一个运行于45MHz的快速现场可编辑逻辑器件。一个基本的DDS系统包括一个数字振荡器（NCO）用来产生输出载波，和一个数模转换器（DAC）用来将从NCO过来的数字式正弦曲线字产生一个抽样的模拟载波。当DAC的输出是根据参考时钟频率的抽样时，通常用一个圆滑波形的低通滤波器来消除混叠成分。根据输入的参考时钟抽样经过NCO来产生输出载波。NCO的基本构成是一个相位累加器和一个正弦ROM查找表。通过增加NCO的载波相位调制的输出能力可以提高DDS系统的设计。为了更好的理解NCO设计的各种功能，首先考虑仅包括一个相位累加器和一个正弦ROM查找表的基本NCO设计。与欧拉公式（Euler’sformula）图解比较就能最好地理解这两个表的NCO设计的功能。欧拉公式的图解如图3所示，是一个单位向量绕着实轴和虚平面的中心以Wrad/s的速度转圈。这个频率控制字是最后一个抽样相位值通过一个N位加法器的连续地累加而成。加法器的输出是参考抽样时钟通过一个N位寄存器的抽样。当累加器达到N位最大值的时候，累加器翻转然后继续。然后相位累加器的抽样输出用来在一个正弦量化值表里进行查找。抽样相位到正弦量化的转化可以看作是真实的或者虚拟的成分及时地影射。因为相位累加器的比特位数决定了频率调整的步进，一个典型的相位累加器的大小是24到32位。由于正弦ROM表的大小是跟寻址范围直接成比例的，因此，不是所有相位累加器的24或32位都用来作为正弦ROM表的地址。仅是相位累加器的高Y（Y〈N〉位是用来作为正弦ROM表的地址，Y通常不必要等于正弦ROM表的输出量位D。因为一个NCO输出的一个基于一个数字表示的相位和正弦波量化形式的载波，所以设计者可以完全的控制输出载波的频率，相位和幅度。通过加入一个相位端口和一个相位加法器到一个基本的NCO设计中，NCO的输出载波当M等于相位端口数和M小于或等于Y（用来作为正弦ROM表的地址位数）时可以被M矩阵相位调制。假如系统设计需要幅度调制如QAM，可以加入一个量化端口来调整正弦ROM表的输出。注意到这个端口没有在图2里表示出来以及这个特色没有在简单的快速逻辑FPGA设计中论证。最后，频率是调制是一个基本的NCO设计给出的。因为频率控制字是跟抽样时钟是同步装载到DDS的，频率的转化是相位连续的。虽然DDS系统给设计者完全地控制复杂的调制合成，但是在一个非线性数字格式的正弦相位和量级的表示却是复杂的新设计。在取样任何的连续时间信号时，必须考虑取样原理和量子化误差。为了理解DDS系统中取样理论的效果，最好看一下时间和频率域的DDS合成过程。就象上面规定的，通过以指定的速率累积的形式由NCO产生一个正弦波然后用一个相位的值来定位一个正弦调制ROM表的值。因此，NCO本质上用一个正弦波和用NCO的上升或下降沿输出参考取样时钟对其取样。图4表示在时间和频率域里NCO的处理。注意到这个表示并非量子化假设。基于频率控制字的装载，NCO在一个时期内提供一批幅度的输出值。这个正弦曲线的频率域表示在指定的频率里是一个推动的作用。N