quartus经典时序分析器优先级2

MulticycletimingassignmentRelaxesthesetuprelationshipbyallowingyoutospecifythenumberofdestinationclockcyclesrequiredbeforearegisterlatchesavalue.Thisassignmentmaybehelpfulinachievingtimingrequirementsindesignsbyaddingdestinationclockcycles.Forexample,assigningaMulticyclevalueof2toaclockedregisterdelaysthelatchedgebyonedestinationclockcycle,asshowninfigure1.Figure1YoucanassigntheMulticycletimingassignmentbetweenaspecificsourceanddestination,ortoallvalidnodesincludedinawildcardorassignmentgroupassignment.Thevalueofthisassignmentmustbeapositivenumbergreaterthanzero.Bydefault,theClassicTimingAnalyzerassumesthattheDefaultMulticycleHoldsettingisthesameastheMulticyclesetting.Therefore,ifyouassignaMulticycle,SourceMulticycle,ClockEnableMulticycle,and/orClockEnableSourceMulticycleassignment,thecorrespondingholdrequirementissimilarlychangedunlessyouspecifyaspecificvaluefortheholdrequirement.Thefollowingtableprioritizeseachlegalassignmenttype,andshowswhichpathsareaffectedwhenassigned.Priority1assignmentstakeprecedenceoverpriority2assignments,andsoon.Withinaprioritylevel,themoststringentrequirementtakesprecedence.Specifyingapoint-to-pointMulticycleassignmentmayincreasethetimenecessaryfortiming-drivencompilation.PriorityLevelAssignmentAffectedPath(s)Type/Location1Point-to-pointAlldatapathsfromthesourcetodestinationnode.assignmentfromregistertoregister.Point-to-pointassignmentfrominputorbidirectionalpintoregister.Point-to-pointassignmentfromregistertooutputpin.Single-point23Alldatapathsassignmenttoorfromterminatingattheanyregisters.specifiednode.Point-to-pointassignmentfromclocktoclock.Allpathswithsourceclockedbyclk1andallpathswithdestinationclockedbyclk2.4Single-pointAllpathsclockedbyassignmenttoaclockthespecifiedclock.MulticycleHoldtimingassignmentRelaxestheholdrelationshipbyallowingyoutospecifytheminimumnumberofdestinationregisterclockcyclesrequiredbeforearegisterlatchesavalue.Whenthesourceanddestinationclockshavedifferentfrequencies,thisassignmentallowsyoutoincreasetherequiredholddelaybyaddingdestinationclockcycles.Forexample,ifyouassignaMulticycleHoldrequirementof2toaclockedregister,thesignalmusttravelfromthesourcetothedestinationregisterinnolessthannegativeoneclockcycleinordertomeettherequirement.Thisassignmentmaybehelpfulincorrectinginternalholdviolationscausedbyclockskew.Figure1showshowassigningaMulticycleHoldvalueof2affectstheholdrelationship.Figure1YoucanassigntheMulticycleHoldtimingassignmentbetweenaspecificsourceanddestination,ortoallvalidnodesincludedinawildcardorassignmentgroupassignment.Bydefault,theClassicTimingAnalyzerassumesthattheDefaultMulticycleHoldsettingisthesameastheMulticyclesetting.Therefore,ifyouassignaMulticycle,SourceMulticycle,ClockEnableMulticycle,orClockEnableSourceMulticycleassignment,thecorrespondingmulticycleholdrequirementissimilarlychangedunlessyouspecifyaspecificvaluefortheholdrequirement.Thefollowingtableprioritizeseachlegalassignmenttype,andshowswhichpathsareaffectedwhenassigned.Priority1assignmentstakeprecedenceoverpriority2assignments,andsoon.Withinaprioritylevel,themoststringentrequirementtakesprecedence.Specifyingapoint-to-pointMulticycleHoldassignmentmayincreasethetimenecessaryfortiming-drivencompilation.文章来源：重心网络版权所有PriorityLevelAssignmentAffectedPath(s)Type/Location1Point-to-pointAlldatapathsfromthesourcetodestinationnode.assignmentfromregistertoregister.Point-to-pointassignmentfrominputpinorbidirectionalpintoregister.Point-to-pointassignmentfromregistertooutputpin.23Single-pointassignmenttoanyregister.Alldatapathsterminatingatthespecifiednode.Point-to-pointassignmentfromclocktoclock.Allpathswithsourceclockedbyclk1andallpathswithdestinationclockedbyclk2.4Single-pointAllpathsclockedbythespecifiedclock.assignmenttoaclockSourceMulticycletimingassignmentRelaxesthesetuprelationshipbyallowingyoutospecifythenumberofsourceclockcyclesrequiredbeforearegistershouldlatchavalue.Thisassignmentmaybehelpfulinachievingtimingrequirementsindesignsbyaddingsourceclockcycles.Forexample,assigningaSourceMulticyclevalueof2toaclockedregisterdelaysthelatchedgebyoneclockcycle,asshowninfigure1.Figure1.YoucanassigntheSourceMulticycletimingassignmentbetweenaspecificsourceanddestination,ortoallvalidnodesincludedinawildcardorassignmentgroupassignment.Thevalueofthisassignmentmustbeapositivenumbergreaterthanzero.Bydefault,theClassicTimingAnalyzerassumesthattheDefaultMulticycleHoldsettingisthesameastheMulticyclesetting.Therefore,ifyouassignaMulticycle,SourceMulticycle,ClockEnableMulticycle,orClockEnableSourceMulticycleassignment,thecorrespondingholdrequirementissimilarlychangedunlessyouspecifyaspecificvaluefortheholdrequirement.Thefollowingtableprioritizeseachlegalassignmenttype,andshowswhichpathsareaffectedwhenyoumakethisassignment.Priority1assignmentstakeprecedenceoverpriority2assignments,andsoon.Withinaprioritylevel,themoststringentrequirementtakesprecedence.Specifyingapoint-to-pointSourceMulticycleassignmentmayincreasethetimenecessaryfortiming-drivencompilation.PriorityLevelAssignmentType/LocationAffectedPath(s)1Point-to-pointassignmentfromregistertoregister.Alldatapathsfromthesourcetodestinationnode.Point-to-pointassignmentfrominputorbidirectionalpintoregister.Point-to-pointassignmentfromregistertooutputpin.23Single-pointassignmenttoanyregister.Alldatapathsterminatingatthespecifiednode.Point-to-pointassignmentfromclocktoclock.Allpathswithsourceclockedbyclk1andallpathswithdestinationclockedbyclk2.4Single-pointassignmenttoaclock.Allpathsclockedbythespecifiedclock.SourceMulticycleHoldtimingassignmentRelaxestheholdrelationshipbyallowingyoutospecifytheminimumnumberofsourceregisterclockcyclesrequiredbeforearegisterlatchesavalue.Whenthesourceanddestinationclockshavedifferentfrequencies,thisassignmentallowsyoutoincreasetherequiredholddelaybyaddingsourceclockcycles.Forexample,ifyouassignaSourceMulticycleHoldrequirementof2toaclockedregister,thesignalmusttravelfromthesourcetothedestinationregisterinnolessthannegativeonesourceclockcycleinordertomeettherequirement.Thisassignmentmaybehelpfulincorrectinginternalholdviolationscausedbyclockskew.GuidelinesFigure1showshowassigningaSourceMulticycleHoldvalueof2affectsthedefaultholdrelationship.Figure1.YoucanassigntheSourceMulticycleHoldtimingassignmentbetweenaspecificsourceanddestination,ortoallvalidnodesincludedinawildcardorassignmentgroupassignment.Bydefault,theClassicTimingAnalyzerassumesthattheDefaultMulticycleHoldsettingisthesameastheMulticyclesetting.Therefore,ifyouassignaMulticycle,SourceMulticycle,ClockEnableMulticycle,orClockEnableSourceMulticycleassignment,thecorrespondingholdrequirementissimilarlychangedunlessyouspecifyaspecificvaluefortheholdrequirement.Thefollowingtableprioritizeseachlegalassignmenttype,andshowswhichpathsareaffectedwhenassigned.Priority1assignmentstakeprecedenceoverpriority2assignments,andsoon.Withinaprioritylevel,themoststringentrequirementtakesprecedence.Specifyingapoint-to-pointSourceMulticycleHoldassignmentmayincreasethetimenecessaryfortiming-drivencompilation.PriorityLevelAssignmentType/LocationAffectedPath(s)1Point-to-pointassignmentfromregistertoregister.Alldatapathsfromthesourcetodestinationnode.Point-to-pointassignmentfrominputorbidirectionalpintoregister.Point-to-pointassignmentfromregistertooutputpin.2Single-pointassignmenttoanyregister.Alldatapathsterminatingatthespecifiednode.34Point-to-pointassignmentfromclocktoclock.Allpathswithsourceclockedbyclk1andallpathswithdestinationclockedbyclk2.Single-pointassignmenttoaclock.Allpathsclockedbythespecifiedclock.ClockSetupUncertaintytimingassignmentAllowsyoutospecifytheexpectedclocksetupuncertaintyassociatedwithjitter,skew,andaguardbandwhenperformingsetupchecks.YoucanusetheAssignmentEditortoassigntheClockSetupUncertaintyassignmenttoaclocksignal,orasapoint-to-pointassignmentbetweentwoclocks.Afterassigningthisrequirement,theClassicTimingAnalyzersubtractsthespecifiedclocksetupuncertaintyfromthedatarequiredtimewhencalculatingsetupchecks,andreportsthiswithotherdataintheClockSetuptiminganalysisreport.ClockHoldUncertaintytimingassignmentAllowsyoutospecifytheexpectedclockholduncertaintyassociatedwithjitter,skew,andaguardbandwhenperformingholdchecks.YoucanusetheAssignmentEditortoassignthisrequirementtoasingleclocksignal,orasapoint-to-pointassignmentbetweentwoclocks.Afterassigningthisrequirement,theClassicTimingAnalyzeraddsthespecifiedholduncertaintytothedatarequiredtimewhencalculatingholdchecksandreportsthiswithotherdataintheClockHoldtiminganalysisreport.EnableclocklatencyDirectstheClassicTimingAnalyzertoanalyzethelatencybetweenrelatedclocks,ratherthantheoffset.Clocklatencyrepresentssimpledelayontheclockpath(whichaffectsclockskew),ratherthanoffset(whichaffectsthesetuprelationshipandholdrelationship).Whenthisoptionisturnedon,theClassicTimingAnalyzerreportsauto-detectedoffsetaslatency,reportsthecompensationdelayofPLLsaslatency,andappliesanyEarlyClockLatencyorLateClockLatencytimingassignments.TheClassicTimingAnalyzerreportstheresultsofclocklatencychecksasclockskewintheTimingAnalyzerreports.EarlyClockLatencytimingassignmentSpecifiesadditionaldelay(latency)inaclocknetwork.Thisdelayrepresentstheexternaldelayfromavirtual(ideal)clockthroughtheshortestpath.TheClassicTimingAnalyzerusesthemoreconservativelatencyvalue.Forsetupanalysis,theClassicTimingAnalyzerusestheearlylatencyvalueforeachdestinationregister.Forholdanalysis,theClassicTimingAnalyzerusestheearlylatencyvalueforeachsourceregister.YoucanassigntheEarlyClockLatencytimingassignmenttoaclocksignalinthedesign.TodirecttheClassicTimingAnalyzertoreporttheresultsofclocklatency,youmustturnontheEnableClockLatencyoptionintheMoreTimingSettingsTimingAnalyzerfolderoftheCompilationReport.TheClassicTimingAnalyzerignoresearlyandlateclocklatencyonaclockwhenanalyzingpathsbetweenregisterswithinthesameclockdomain.Figure1showsthea