EMC设计基础及经验

Introduction

to

EMCDesign

EMCDesignCenterPreparedbyTankLaitank_lai@OutlineMechanismofEMCEMCproblemmitigationEMCcriticalconceptPCBDesignMechanicalDesign透過電感、電容耦合的輻射干擾或傳導干擾MechanismofEMCNoiseSourceCouplingpathSusceptorSusceptibility:ImmunityEMCproblemmitigation降低雜訊源所產生的雜訊能量Ex:SpreadSpectrum,Reducedrivinglevel…截斷雜訊源與被干擾者之間的干擾途徑Ex:Addnoisefilter,groundisolation…增強被干擾者對電磁的抗干擾能力

Ex:Addshieldedcover,softwareadjustment…Impedanceathighfrequency降低迴路的自感與互感&利用電容縮小高頻迴路面積;利用電阻與感抗降低雜訊電流!Returnpath預先規劃好高頻迴路路徑!Antenna破壞電場(rod)與磁場(loop)天線;EMI與EMS其實是一體兩面,就像天線容易發射就容易接收!EMCcriticalconceptNofrequency,NoEMI

&

EMS!ImpedanceathighfrequencyV

雜訊電壓=I雜訊電流XZ

阻抗Z=R+jωL+1/(jωC),ω=2πf阻抗=電阻

+

感抗+容抗

零相位正相位負相位就EMI常見問題都是電感L造成的效應!Ltotal=Lselfinductance+Lmutualinductance

元件,trace

+電流迴路電流就像水流ImpedanceathighfrequencyV

雜訊電壓=I雜訊電流XZ

阻抗水壓(V)causedby

水流量(I)

&

水道阻力(Z)Z=R+jωL+1/(jωC),ω=2πfR:水道,R大水道小L:有彈力的水車(放在水道中),L大水車彈力大C:儲水槽(與水道並排),C大水槽大ω:水流速度Impedance

ofCapacitorsImpedanceathighfrequencyAnti-resonance:0.01μ電容的電感效應區與100p電容的電容效應區結合成LC並聯線路,造成高阻抗(反共振點),所以電容不應集中在一處!ImpedanceathighfrequencyFerriteBead特性曲線圖:

(曲線恰巧與電容相反)等效電路ImpedanceathighfrequencyGNDplane立體示意圖為什麼不能跨切割?跨切割迴路面積會很大Noisesourcesignaltrace完整ImagePlaneImagePlane有moat時ReturnpathReturnpathPVC-R4.3”實例平面波:定阻抗AntennaRodantenna:輻射電場Zw=E/H1/r@airLoopantenna:輻射磁場Zw=E/Hr@air

Zw

Antenna縫隙天線=rod天線的互補狀態

開孔長度=天線長度理想的法拉第籠FaradayCage不會洩漏電磁波Basedon疊加原理

superpositionprinciple:金屬殼的開孔=理想的法拉第籠-與開孔長度相同的天線

=

-

Antennarod天線的互補狀態即電場變磁場,磁場變電場AntennaPCBDesignGoodcomponentplacementGoodroutingtopologyGoodimpedancecontrol(阻抗匹配)GoodpowersystemarrangementGoodandsolidgroundplaneGoodSI/PIGoodEMIperformance1.ReserveLCfilter

inMSCLK,MSDATA,KBCLKandKBDATAattheendnearPS2connector.SchematicsPS2port2.ReserveLCfilteronsignallinenearserialportconnector.Serialport(RS232)3.ReserveLCfilteronsignallinenearparallelportconnector

Parallelport4.ReserveπtypefilteronRGBsignalnearD-Subconnector

D-Subport5.Reservecap.(atC1andC2location)andcommonmodechoke(atL1)andlocatethemascloseaspossibletoUSBconnector

USBportFordifferentialsignals6.ReserveLCfilteroneachpowerpinofCLKgeneratorandclockbufferClockIC7.Reservedecouplingcap.oneachpowerpinascouldaspossible,ofKeycomponent,e.g.,NB,SB,Video,LAN,Memoryslot,PCI-Eslot,etcKeycomponent8.Reservebypassingcap.oneachsignalofcrystaland/oroscillatorcircuitOscillatorCrystal9.ReservedecouplingcaponeachpowerinputpinonpowerconnectorascouldaspossiblePowerconnector10.Reserve0.1UcaponpowersupplysignaltracetopreventtransientnoiseraisedatSurgetestthroughPSUintopowersupplysignal,e.g.powergood,onPCBAtoimpactotherlogiccircuitPowergoodTheclockgeneratorandhigh-speedcomponentsshouldbe

asfaraspossibleawayfromI/OareaandPCIslotsPlacement2.Locaterelationalchiptomakedirectroutingofclocksandhighspeedsignalsaswellasshortaspossible

3.Arrangeanydaughtercardand/ormoduleawayfromhighspeedarea

4.LocateLCfilter

reservedforKB/MSportsveryneartotheKB/MSconnector5.LocateLCfilter

reservedforSerialportsveryneartotheSerialconnector6.LocateΠ-typeorT-typefilterforRGBsignalveryneartoD-Subconnector7.LocateLANchipascloseaspossibletoLANconnectortomakethedirectroutingasshortaspossible8.Thedistancebetweenchippowerpinanddecouplingcapshouldbeanomorethan100mils

andthewidthoftraceconnectingpowerpinandbypasscapshouldbeatleast20mil9.Thedistancebetweenchipgroundpinandgroundviashouldbenomorethan40mils

andthetracewidthshouldbeatleast20mil10.KeepsensitivecomponentawayfromtheboardedgeofPCBatleast20timesthethicknessbetweensignallayerandthereferencelayer

11.LocateESDsuppressor,e.g.,RCnetwork,LCfilter,diode,varistor,etc.,atthecriticalI/Osignal12.ReserveESDstripalongboardedgetopreventthecriticalcircuitfromdamageofESD(ifNOmetalenclosure)Routing1.Use3-Wrule

betweenI/Otracesandclock/high-speedtracestokeepcrosstalkdown2.Ifchanginghigh-speedgroupsthatreferenceavoltageplane,aviaconnectingthevoltageplanesshouldbelocatedwithin50milsofthetransition.IfthevoltageplanesdonotsharethesameDCvoltage(includingground),thentwobypasscapacitorsshouldbeplacedwithin100milsofthetransition3.Donotroutealongboardedges.Allhigh-speedsignalsshouldberemovedfromtheedgeatleast20timestheheighttothenearestgroundplane4.MultipointgroundshouldbeusedwhereESDcurrentflowisdesired5.HighSpeedrouting(e.g.,clocksignal,differentialpairs,databus)can’tcrossanymoatoftheimageplane,e.g.powerorgroundplane6.IfroutingCLKsignaltracesoverasplitpowerplane,please

reserveadecouplingcap

betweendifferentvoltageplanetosupportareturnpathtoRFcurrent7.Routethehighspeedsignalonlyontheroutinglayerrefertoasolidgroundplane

ascouldaspossible8.Allownomorethan4viasoneachhighspeedroute,e.g.clocksignal,differentialsignal9.Differentialsignalshouldrouteparalleltoeachotherfromsourcetoreceiverendandclosetoeachotheraspossibleascould.10.AllsignalsinapairshouldhaveequaltracelengthonEACH

routinglayer.

Pairlengthsshouldbematchedwithin10milson

eachroutinglayer,and10milsoverall.

11.Ifchanginghigh-speedbusbecomesnecessarytheninclude

agroundviawithin50milsofeachtransition.

Groundviascanbesharedfor3or4signalsonthebus12.Ifchanginghigh-speeddifferentialsignalsbecomesnecessarythenincludeagroundviawithin50milsofeachtransition.Groundviacanbeshared13.Locateendterminationwithin500milsofthefinalreceiver

14.UseabridgebetweenananalogandadigitalareaunderAudio

CODEC.UsearesistororcapacitortolinktheGNDneartheotherI/Oconnector15.AguardbandshouldbeprovidedinthePCBdesign.Andthereisnosolder-maskonit16.Keeptheroutingofhighspeedandcriticalsignalawayfromthekeepoutareaskewholeatleast20milstopreventESDRFcurrentcouplingtothesehighspeedtracePowerplaneandGroundplane1.VCCareafieldisbetterthanapowertraceespeciallyforahigherloadingpowerandaddeachviasupplies200mA

2.PuttheVCCfillatbottomsideandGNDfillattopsideforaclockgenerator

3.Checktheproperpowerflowasplanningpowerplanesforeachvoltagerequirementbasedontherequiredcurrent4.Theanalogpowershouldbeisolatedfromdigitalonebyafilter(FerriteBead)5.Minimizeinductanceoftheloopformedfromthepowerpin,usingthebypasscapacitorandleadnoisetothegroundpin6.High-speeddesignsgenerallyrequireuseofmultiplegroundconnections7.Tokeeptheinnergroundlayerasawholesolidplane

andtheonlyexceptionisforEthernetandModemPortareaPS:Isolationisnecessaryforelectricstrength(Hi-pot)8.Ahigh-speedsignalshouldhaveanadjacentgroundreturnpinsonallsidesoftheconnectororinterface10.Tokeepgroundviasconnectingdifferentisolatedgroundplaneontopandbottomsidetoinnergroundlayer

MechanicaldesignReduceAntennaeffectSupportgoodshieldingLowsurfaceimpedance(lessthan50μOhm)WellcontactbetweenmetalsubpartsGoodcabledesignGoodinterconnectingMitigatingantennaeffectWhereexistantennastructure?Heatsink,seam,slot,aperture,cabling,chip,etc..Howtomitigatetheantennaeffect?GoodgroundingGoodopeningdesignGoodcableroutingDonotmakecablingexposedoutsideetc..Shieldingeffectiveness屏蔽效應的大小金屬屏蔽FaradayCage可以隔絕NOISESOURCEemissionimmunityWhatisSEShieldingeffectiveness(SE)SE=20log(E2/E1)WhereE2istheelectricfieldasnon-shieldingandE1istheelectricfieldasshieldingSE=A+R+MA:absorptionloss(positivevalue)~δR:reflectionloss(positivevalue)~ηM:additionaleffectofmultiplere-reflectionandtransmission由圖可知,金屬屏蔽厚度越大吸收損耗(A)越好SEofdifferentmaterial&thick導電性越好近場反射損耗(R)越大反射損耗:銅>鋁>鋼SEofdifferentmaterial開孔的長度

(例如機殼狹縫）開孔的重要性比屏蔽材質來的大決定洩漏量的因素1.開孔長度

(開孔長度越長,感應電流繞越遠)2.WaveImpedance 3.Source的頻率開孔長度與屏蔽效應的關係若開孔長度小於或等於/2時(亦即開孔長度在/20以下,可產生20dB以上的屏蔽效果)*以1GHz為例,若開孔為1.5cm,S=20dB ,若開孔為2cm,S=17.5dBOpeningdesign金屬屏蔽的重疊效應

金屬屏蔽重疊可增加其電容值 因此可以達到高通的效果 增加高頻的屏蔽率

另外藉由重疊的效果 亦能增加電磁波繞射的距離與衰減PS:塑膠件的重疊設計,可以加長ESD的放電路徑,增加隔離效果!Cabledesign-----PindefineCabledesign-----shieldandgrounding線材shield的接地線材shield兩端接地為較佳的設計可減少磁場耦合到其他線材(但若有外界雜訊干擾使shield成為雜訊迴路亦可能造成反效果)兩端接地才能形成迴路電流BraidedShield優點:1.有彈性2.耐用3.強度夠4.收縮性好5.容易做到360°terminationoftheshield缺點:1.一般只有提供60~98%覆蓋效果特性:1.電場屏蔽效果較差(電容性)PS:300MHz~30GHz除外(UHF)原因:BraidedShield容易變形

2.磁場屏蔽效果較好(電感性)PS:但比FoilShield的效果差了5~30dB左右FoilShield優點:1.可提供100%覆蓋效果缺點:1.不耐用2.有較高的截止頻率(例如鋁箔:7kHz)3.比較困難做到360°terminationoftheshieldPS:我們可將上述兩者合併一起利用,截長補短,但價格較貴,製程較繁雜BraidedandfoilshieldingPigtaileffect影響:Pigtails接法的好壞,對磁場屏蔽效果影響頗大要求:Pigtails必須均勻的包圍connector端，這樣磁場屏蔽效果才會好例子:像BNC,UHF,TypeNconnector都提供360°覆蓋的connectorPS:如果不用上述的connector,也有另一方法,如Figure2-35所示符合transmissionlinemodel的條件:λ(波長)<<L

(Cable的長度)易形成駐波,天線效應佳,接收效果也好不易形成駐波,天線效應差,接收效果也差Cable的長度小於λ/10時,耦合量與長度的對數成正比TransmissionLineModel的長度若為/4的奇數倍,是最佳的發射與接收長度。EffectofcablelengthExamples1.Toaddenoughdimplestominimizethelengthofseam/slot,whichbetweentheuppercoverandbasechassisandthedistancebetweendimpleshouldbenomorethan2cm

2.Enhancecontactpressurebetweenupperandlowercovers3.Addenoughdimplesonraisercardholdertowellcontacttopcover4.UsemetalspringsmountedontheinsideofchassiswalltowellcontactthemetalshieldofI/Oconnectortoprovideagoodgrounding5.Ifpossibleandcostallowed,usinggasket-likeI/Oshieldtoreplacetinplate馬口鐵I/Oshieldtomakecontactmorestably

6.It’sbettertomountcopperspringfingersonsystemboxtowellcontacttheraisercardholder7.Clipcontactisbetterthanspring(housingmaterial)contact8.MountcopperspringfingersonmetalshieldofHDD/ODDholdertowellcontacttopcover9.Keepallinterconnectcablestorouteinsidemetalboxascouldaspossible.Otherwise,makesurethecablesexploredoutsidethemetalboxhaveagoodshieldingandgroundingtosystemchassistosuppressradiatedemissionpickedupbytheseexploredcables10.UsingFaradaycagetocoverhigh-speeddaughtercard/moduleandatleastreservefourscrewstogroundtoPCBA11.Forproductonlyassembledwithplasticenclosure.Itshouldkeep8mmdistancebetweenallconductiveparts,e.g.PCBAandthes