数字电路第六章课件

Chapter6

CombinationalLogicDesignPractices组合逻辑电路ChapterOutlineDocumentationStandardsDigitalCircuitTimingandPropagationdelayCombinationalLogicDesignStructures

:

-Decoders

-Encoders

-Three-StateBuffers

-Multiplexers

-EXCLUSIVEORGatesandParityCircuits

-Comparators

-Adders/Subtractors

-ArithmeticLogicUnits(ALUs)6.1DocumentationStandard

(文档标准)Documentationofadigitalsystemshouldprovidethenecessaryinformationforbuilding,testing,operating,andmaintainingthesystem.Specification:DescriptionofInterfaceandFunction

(说明书：接口及功能描述)BlockDiagram:System’sMajorFunctionModuleandtheirBasicInterconnections

(方框图：主要功能模块及其互联P345图6-1)SchematicDiagram:showingallthecomponents,theirtypes,andallinterconnections

(原理图（P360图6-17）)BlockDiagramSchematicDiagramHierarchichalschematicstructureDocumentationStandard

(文档标准)TimingDiagram:showingthelogicsignalsasafunctionoftime

(定时图（P363图6-19）)StructureLogicDeviceDescription:showingtheoperationofthestructures

(结构化逻辑器件描述)CircuitDescription:Explainshowthecircuitworksinternally.

(电路描述：解释电路内部如何工作)“HierarchicalDesign”GateSymbols(门的符号)&≥11DeMorganequivalentsymbols

(等效门符号（摩根定理）)Inverter(反相器)Buffer(缓冲器)Whichsymboltouse?－dependsonsignalnamesandactivelevels.SignalNamesandActiveLevels

(信号名和有效电平)Signalname:adescriptivealphanumericlabelforeachinput/outputsignal.Inrealsystem,well-chosennamesconveyinformationtoreadersEachsignalnameshouldhaveanactive-levelassociatedwithit.

(有效电平)ActiveHigh

（高电平有效）ActiveLow

（低电平有效）READYREQUESTGOREADY_LREQUEST_LGO_LSignalNameandActiveLevels

(信号名和有效电平)Thesignalisasserted

whenitisinitsactivelevelandnegated(ordeasserted)whenitsnotinitsactivelevel.AnInversionBubbletoIndicateanActive-LowPin(有反相圈的引脚表示低电平有效)Activelowsignalhasasuffixof_L

aspartofthevariablename.SignalNameandActiveLevels

(信号名和有效电平)ENABLEDOMYTHING……………ENABLEDOMYTHING……………

AND,OR,andalarge-scalelogicelementhaveactive-highinputsandoutputsThesameelementswithactive-lowinputsandoutputsGivenLogicFunctionasOccurringinsidethatsymbolicoutline.(给定逻辑功能只在符号框的内部发生)Bubble-to-BubbleLogicDesign

(“圈到圈”的逻辑设计)Purpose:TomakeiteasytounderstandthefunctionoftheLogiccircuitbychoosingappropriatelogicsymbolsandsignalnamesincludingactive-leveldesignators.

ERRORFAIL_LOVERFLOW_L

ERRORFAIL_LOVERFLOW_LBubble-to-BubbleLogicDesign

(“圈到圈”的逻辑设计)AASELBDATAAASELBADATA_LBDATA_LDATA6.2CircuitTiming(电路定时)PropagationDelay(传播延迟)--ASignalPathastheTimethatittakesforaChangeattheInputtoProduceaChangeattheOutputofthePath(信号通路输入端的变化引起输出端变化所需的时间)tpHLandtpLHMaybeDifferentPropagationDelayTimingAnalysis:Worst-CaseDelay(定时分析：取最坏情况延迟)MaximumDelay(最大延迟)TypicalDelay(典型延迟)MinimumDelay(最小延迟)’08’08’04’32’32’32P366表6-2152022226.2CircuitTiming(电路定时)TimingDiagram定时图（时序图）GOREADYDAT6.2CircuitTiming(电路定时)CausalityandPropagationDelay(因果性和传播延迟）GOREADYDATtDATtDATtRDYtRDYGOREADYDAT6.2CircuitTiming(电路定时)TimingDiagram定时图（时序图）MinimumandMaximumDelay(最小和最大延迟）GOREADYDATtRDYmintRDYmax6.2CircuitTiming(电路定时)CertainandUncertainTransitions

(确切的和不确切的转换）WRITE_LDATAOUTDATAINtOUTmaxtsetuptOUTminCommonlyUsedMSICombinationalLogicDeviceDecoders(译码器)Encoders(编码器)Multiplexers(多路复用器)ParityCircuits(奇偶校验)Comparators(比较器)Adders(加法器)DecoderandEncoder

(译码器和编码器)Multiple-Input,Multiple-OutputLogicCircuit(多输入、多输出电路)EnableInputs(使能输入)(输入编码)(输出编码)Map映射EnableInputsmustbeAssertedtoperformNormalMappingFunction(使能输入有效才能实现正常映射功能)InputCodeWordOutputCodeWordDecoder（译码器）

NormallyOutputCodehasMorebitsthanitsInputCode

(一般来说，输出编码比输入编码位数多)Encoder（编码器）

OutputCodehasFewerbitsthanitsInputCodecalledanEncoder(输出编码比输入编码位数少，则常称为编码器)DecoderandEncoder

(译码器和编码器)MostCommonlyUsedCase使能输入编码输出编码Map映射Decoder（译码器）Encoder（编码器）N-BitBinaryCode(n位二进制码)2n

中取1码使能输入编码输出编码Map映射2n中取1码n位二进制码(1-out-of2n)6.4Decoder（译码器）BinaryDecoder

(二进制译码器)1.

2-to-4Decoder2-to-4DecoderY0Y1Y2Y3I0I1EN

0XX00001000001101001011001001111000InputsENI1I2OutputsY3Y2Y1Y0(2-4二进制译码器真值表)TruthTablefora2-to-4BinaryDecoderY0=EN·(I1’·I2’)Y1=EN·(I1’·I2)Y2=EN·(I1·I2’)Y3=EN·(I1·I2)Yi=EN·miDecoder（译码器）

0XX00001000001101001011001001111000InputsENI1I2OutputsY3Y2Y1Y0(2-4二进制译码器真值表)TruthTablefora2-to-4BinaryDecoder2-to-4DecoderThe74x139Dual2-to-4Decoder

(双2-4译码器74x139)1XX1111

00011100011101

0101011

0110111InputsGBAOutputs

Y3_LY2_LY1_LY0_LTruthTableforOne-halfofa74x139Dual2-to-4Decoder74x1391Y01Y11Y21Y31G1A1B2Y02Y12Y22Y32G2A2B12315141345671211109LogicSymbolsforLarge-ScaleElementY0Y1Y2Y3GAB1/274x139Y0Y1Y2Y3GAB1/274x139Y0Y1Y2Y3GAB1/274x139G_LABY0_LY1_LY2_LY3_L00000001000000100000010000001000000100000010000001000000100000003-to-8DecoderI2I1I0Y0Y1Y7Yi=EN·mi1111111011111101111110111111011111101111110111111011111101111111Decoder（译码器）000001010011100101110111I2I1I0Y7Y1Y0Y2Y3Y4Y5Y6(3-8二进制译码器真值表)TruthTablefora3-to-8BinaryDecoder2.

3-to-8DecoderThe74x1383-to-8Decoder

(3-8译码器74x138)低位高位Y0_LY1_LY7_LY2_LY3_LY4_LY5_LY6_LENG1G2A_LG2B_LENEN=G1·G2A·G2B=G1·G2A_L’·G2B_L’Yi=EN·miYi_L=Yi’=(EN·mi

)’ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EnableY6_L=(C·B·A’)’=m6’Logicdiagramforthe74x138用74x138设计4-16译码器CascadingBinaryDecoders

N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_L思路：16个输出需要

片74x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2任何时刻只有一片在工作。4个输入中，哪些位控制片选哪些位控制输入Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?32个输出需要多少片74x138？控制任何时刻只有一片工作 ——利用使能端5个输入的低3位控制输入5个输入的高2位控制片选 ——利用2-4译码器P391图6-37UsedecoderandGatestorealizelogicfunctionF=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5)Binarydecoder：Yi=EN·mi

Enableinputsareasserted:

Yi=mi

Yi_L=Yi’=mi’=MiABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138UsedecoderandGatestorealizelogicfunctionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF=(X,Y,Z)(0,3,6,7)当使能端有效时Yi=miUsedecoderandGatestorealizelogicfunctionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF=(X,Y,Z)(0,3,6,7)=M1·

M2·M4·M5=m1’

·

m2’

·m4’

·m5’F=(X,Y,Z)(1,2,4,5)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFBCDDecoder(二－十进制译码器)Inputs:4-bitBCDcodeOutputs:1-out-of10CodeY0Y9I0I1I2I3多余的6个状态如何处理？输出均无效：拒绝“翻译”作为任意项处理——电路内部结构简单二-十进制译码器00000001001000110100010101100111100010011010101111001101111011110111111111101111111111011111111110111111111101111111111011111111110111111111101111111111011111111110111111111111111111111111111111111111111111111111111111111111I3

I2

I1

I00123456789Y0_L

Y9_L伪码Don’tcareSeven-SegmentDecoders

(七段显示译码器)abcdefgdpNormallyuse

：Light-EmittingDiodes（LED,半导体数码管）Liquid-CrystalDisplay（LCD,液晶数码管）LED显示器件LCD显示器件LEDabcdefgdp公共阴极abcdefgdp公共阳极点阵型显示器笔划段型显示器Inputcode:4-bitBCD输入信号：BCD码（用A3A2A1A0表示）OutputCode:Seven-SegmentCode输出：七段码（的驱动信号）a~g1---On，0---Offabcdefg111111011011010011111Seven-SegmentDecoders74LS48显示字型与输入的对应关系00000001001000110100010101100111100010011010101111001101111011111111110011000011011011111001011001110110110011111111000011111111110011000110100110010100011100101100011110000000A3

A2

A1

A0abcdefg0123456789101112131415A3A2A1A000

01

11

10000111101001100011000111a七段显示译码器的真值表Ya=A3A2A1A0+A3A1+A2A0Yb=A3A1+A2A1A0+A2A1A0KarnaughMapsforBCD-Seven-SegmentDecoder

(BCD-

七段显示译码器的卡诺图)Yc=A3A2+A2A1A0Yd=A2A1A0+A2A1A0+A2A1A0KarnaughMapsforBCD-Seven-SegmentDecoder

(BCD-

七段显示译码器的卡诺图)KarnaughMapsforBCD-Seven-SegmentDecoder

(BCD-

七段显示译码器的卡诺图)Ye=A2A1+A0Yf=A3A2A0+A1A0+A2A1KarnaughMapsforBCD-Seven-SegmentDecoder

(BCD-

七段显示译码器的卡诺图)Yg=A3A2A1+A2A1A0DesignBCD-Seven-SegmentDecoder逻辑抽象，得到真值表输入信号：BCD码（A3A2A1A0）输出：七段码（的驱动信号）a~g1表示亮，0表示灭选择器件类型采用基本门电路实现，利用卡诺图化简采用二进制译码器实现，变换为标准和形式电路处理，得到电路图abcdefg6.5Encoder（编码器）BinaryEncoderA0A1A2I0I1I710000000000010000000010010000001000010000011000010001000000010010100000010110000000011112nInputsnOutputsI0I1I2I3I4I5I6I7A2A1A0(3位二进制编码器的真值表)TruthTablefora8-to-3EncoderGuarantee:

---oneandonlyoneinputwillbeassertedatatime(任何时刻只有一个输入端有效。)1000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二进制编码器的真值表)Encoder（编码器）TruthTablefora8-to-3EncoderthisistheexactoppositeofadecoderA0=I1+I3+I5+I7A1=I2+I3+I6+I7A2=I4+I5+I6+I7Howtodealwithmultiplerequests?---morethanOneInputsareassertedPriority（优先级）1000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二进制编码器的真值表)Encoder（编码器）TruthTablefora8-to-3EncoderA2A1A0IDLEI7I6I5I4I3I2I1I0Inordertowritelogicequationsforthepriorityencoder’soutputswefirstdefineeightintermediatevariablesH0-H7Highest-Priority(数大优先)PriorityEncoder(优先编码器)H7=I7H6=I6·I7’H5=I5·I6’·I7’…H0=I0·I1’·I2’·…·I6’·I7’A2A1A0IDLEI7I6I5I4I3I2I1I0Inordertowritelogicequationsforthepriorityencoder’soutputswefirstdefineeightintermediatevariablesH0-H7Highest-Priority(数大优先)PriorityEncoder(优先编码器)A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7TheIDLEOutputisassertedifNoInputsareasserted.

IDLE=I0’·I1’·…·I6’·I7’输入输出EI_L有效没有输入请求EO_L有效EnableInput有输入请求EI_L有效GS_L有效A2A1A0EI74x148I7I6I5I4I3I2I1I0GSEO54321131211106791415使能输出，用于级联

EO选通输出GSThe74x148PriorityEncoderA2A1A0GSEOEII7I0A2A1A0GSEOEII7I0Q15_LQ8_LQ7_LQ0_LY0Y1Y2Y3GS2个74x148级联为16-4优先编码器输入：由864，需8片74x148每片优先级不同（怎样实现？）保证高位无输入时，次高位才工作——高位芯片的EO端接次高位芯片的EI端用8-3优先编码器74x148级联为64-6优先编码器A2A1A0GSEOEII7I0片间优先级的编码——利用第9片74x148

每片的GS端接到第9片的输入端

第9片的输出作为高3位（RA5～RA3）片内优先级片间优先级输出：6位低3位高3位8片输出A2～A0通过或门作为最终输出的低3位RA2～RA0分析判定优先级电路：（利用74x148）

8个___电平有效输入I0_L～I7_L，_____的优先级最高地址输出A2～A0，____电平有效若输出AVALID高电平有效，则表示_______________A2A1A0GSEOEI74x148I7I0I0_LI7_LA2A1A0AVALID低I0_L至少有一个输入有效高P514题6.53设计优先级电路：（利用74x148）8个输入I0～I7高电平有效，I7优先级最高地址输出A2～A0，高电平有效如果没有输入有效，输出IDLE有效I7I0A2A1A0IDLEA2A1A0GSEOEII7I074x148P514题6.526.6Three-StateDevices

(三态器件)Three-StateBuffer(Three-StateDriver)三态缓冲器（三态驱动器）ThreeStates: ActiveHigh(1)，ActiveLow(0),Hi-Z

Variousthree-statebuffersThree-StateDevices

Three-StateDeviceallowMultipleSourcestoShareaSingle“PartyLine”AslongasOnlyOnedevice“talk”ontheLineatatime

（三态器件允许多个信号源共享单个“同线”，条件是每次只有一个器件工作）

(Figure6-52)TypicalThree-StateDevicesareDesignedSothattheygointotheHi-ZstateFasterthantheycomeoutoftheHi-Zstate.（对典型的三态器件，进入高阻态比离开高阻态的时间快）ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2fighting（冲突）利用使能端进行时序控制三态器件允许信号共享单个“同线”（partyline）典型的三态器件，进入高阻态比离开高阻态快P0P1P7SDATAEN1EN2_L,EN3_Lmax(tpLZmax,tpHZmax)min(tpZLmin,tpZHmin)SSRC[2:0]01237SDATAP0P1P2P3P7DeadTime(截止时间)StandardSSIandMSIThree-StateBuffer

(标准SSI和MSI三态缓冲器)The74x541Octalthree-statebufferA1A2A3A4A5A6A7A8G1G2Y1Y2Y3Y4Y5Y6Y7Y874x541A1A8G1G2Y1Y874x541DB[0:7]A1A8G1G2Y1Y874x541NotationofDataBus（数据总线的表示法）A1B1DIRTransferDatainEitherDirectionsByUsingThree-StateTransceiver(利用三态缓冲器实现数据双向传送)BusTransceiver(总线收发)DIRG_L6.7Multiplexer（多路复用器）DigitalSwitch,Multi-Switch,DataSelector(又称数据开关、多路开关、数据选择器)（缩写：MUX）UnderSelectControllingSignals,SelectOneoftheMulti-InputstotheOutput

(在选择控制信号的作用下，从多个输入数据中选择其中一个作为输出。)MultiplexerENSELD0Dn-1YEnable使能Select选择n个1位数据源数据输出（1位）ENSELD0Dn-1YEnable(使能)Select(选择)NDataSources(n个b位数据源)DataOutput(数据输出)（b位）EN_LCBAYY_L1XXX0000000100100011010001010110011101D0D0’D1D1’D2D2’D3D3’D4D4’D5D5’D6D6’D7D7’(8输入1位多路复用器)TruthTablefora74x1518-Input,1-bitMultiplexerENABCD0D1D2D3D4D5D6D7YY74x15143211514131211109756EN_LCBAYY_L1XXX0000000100100011010001010110011101D0D0’D1D1’D2D2’D3D3’D4D4’D5D5’D6D6’D7D7’(8输入1位多路复用器)TruthTablefora74x1518-Input,1-bitMultiplexerHowtogetalogicequationforaMUXoutput?输入G_LS1X000100001A2A3A4A1B2B3B4B(2输入4位多路复用器)TruthTablefora74x157输出1Y2Y3Y4Y2-Input,4-bitMultiplexerGS1A1B2A2B3A3B4A4B1Y2Y3Y4Y74x157235611101413115479121G_L2G_LBA1Y2Y11XX000000010010001101000101011001111000100110101011

001C02C01C12C11C22C21C32C31C001C101C201C30

02C002C102C202C3(4输入2位多路复用器74x153真值表)4-Input,2-bitMultiplexerTruthTablefora74x153AB1C01C11C21C31Y7417101112132C02C12C22C32G152Y9双4选1ExpandingMultiplexers

(扩展多路复用器)ExpandingBit(扩展位)HowtoRealize8-Input,16-bitMultiplexer?From8-Input,1-bitto8-Input,16-bit

(由8输入1位8输入16位)Need1674x151,EachChipProcess1-bit

(需要16片74x151，每片处理输入输出中的1位)ExpandingMultiplexers

(扩展多路复用器)ExpandingBit(扩展位)Select-InputsConnecttoC,B,AofEachChip(选择端连接到每片的C,B,A)Note:TheFanoutAbilityofSelectfield

(注意：选择端的扇出能力)（驱动16个负载）ENYYABCD0D7ExpandingInputs(扩展数据输入端的数目)Howtorealize32-Input,1-bitMultiplexer

(如何实现32输入，1位多路复用器？)Inputsfrom8to32,Need4chips

(数据输入由832，需4片)HowtocontrolSelectInputs-----ByHighbitplusLowbit.

(如何控制选择输入端？——分为：高位＋低位)ENYYABCD0D7ExpandingMultiplexers

(扩展多路复用器)ExpandingInputs(扩展数据输入端的数目)如何实现32输入，1位多路复用器？HighBitsplusDecoderasSelect

(高位＋译码器进行片选)LowBitsConnecttoC,B,AofeachChip

(低位接到每片的C,B,A)OutputUsingORGate(4片输出用或门得最终输出)ENYYABCD0D7ExpandingMultiplexers

(扩展多路复用器)Dual4-to-1Multiplexerto8-to-1MultiplexerD0D1D2D3D4D5D6D7A0A1A2YAB1C01C11C21C31Y7417101112132C02C12C22C32G152Y9UseMUXtodesigncombinationalcircuitWhenenableinputisasserted，CanonicsumENABCD0D1D2D3D4D5D6D7YY74x151CBAVCCF实现逻辑函数F=(A,B,C)(0,1,3,7)对比Ex：Use4-to-1MUXtorealize:解：观察逻辑逻辑函数表达式，每个与项都包含了变量A和C，因此用A、C作数据选择器的选择输入端，变换逻辑函数表达式如下MUXD0D1D2D3A0A1ENY对比：四选一MUX表达式令A1=A，A0=CEN’=0，D0=0，D1=D，D2=B，D3=B’YZWX00

01

11

10000111101111111YWX000111100110ZZZZZ’0Use74x151torealizethefunction:F=(W,X,Y,Z)(0,1,3,7,9,13,14)降维：由4维3维ENABCD0D1D2D3D4D5D6D7YY74x151VCCYXWFZ利用74x151实现F=(W,X,Y,Z)(0,1,3,7,9,13,14)0

2

6

41

3

7

5YWX000111100110ZZZZZ’0说明：用具有n位地址输入端的多路复用器，可以产生任何形式的输入变量数不大于n+1的组合逻辑函数。UseMUXtorealizelogicfunction

——Karnughmaps1、将卡诺图画成与数据选择器相适应的形式。也就是说，所使用的数据选择器有几个地址选择输入端，逻辑函数卡诺图的某一边就应有几个变量，且就将这几个变量作为数据选择器的地址选择码

2、将要实现的逻辑函数填入卡诺图并在卡诺图上画圈。顺着地址选择码的方向画圈

3、求输入数据端的逻辑函数表达式。4、根据选择端和输入数据端的逻辑函数表达式，画出用数据选择器实现的电路。Ex.Use4-to-1MUX74x153

and8-to-1MUX74x151torealizethefunctionrespectively.F(A,B,C,D)=∑m(0,1,5,6,7,9,10,13,15)+∑φ(4,8,11,12)

Solution1:4-to-1MUX74x153AB00011110000111100111101Φ11011CDΦ

ΦΦD0=C’

D1=1D2=1D3=DEN

0

1

2

3

Y1

EN

0

1

2

3

Y2

C_L

1

1

D

MUXB

A

0

FA1A0Solution2:8-to-1MUX74x151EN0123Y456711A0MUXDC0B01A_L1FA0A1A2110111101100111011ABCD010000010110101100Φ11ΦΦΦDemultiplexer（多路分配器）Routethebusdatatooneofmdestinations

(把输入数据送到m个目的地之一)多路复用器SRCASRCBSRCZ多路分配器BUSDSTADSTBDSTZSRCSELDSTSELDST:destinationSRC:sourceSEL:selectAbinarydecoderwithanenableinputcanbeusedasademultiplexer(利用带使能端的二进制译码器作为多路分配器)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138DST0_LDST7_LEN_LDSTSEL0DSTSEL1DSTSEL2地址选择——Enableinputisconnectedtothedataline

(利用使能端作为数据输入端)数据输入SRCEN_LCanyoutellthecircuitfunction？6.8ParityCircuit

(奇偶校验电路)Odd-ParityCircuit（奇校验电路）Outputis1ifanoddnumberofitsinputsare1.

(如果输入有奇数个1，则输出为1。)Even-ParityCircuit（偶校验电路）Outputis1ifanevennumberofitsinputsare1.

(如果输入有偶数个1，则输出为1。)回顾：用什么可以判断1的个数？？？ParityCircuitA0A1…An=

1变量为1的个数是奇数0变量为1的个数是偶数Outputofodd-paritycircuitisinverted,wegetaneven-paritycircuit.(奇校验电路的输出反相就得到偶校验电路)NXORgatesmaybecascadedtoformacircuitwithn+1inputsandasingleoutput.(n个异或门级联，形成具有n+1个输入和单一输出的电路)

ReviewofXORANDXNORAB=(A⊙B)’AB’=A⊙BAB=A⊙B’Anytwosignals(inputsoroutput)ofanXORorXNORgatemaybecomplementedwithoutchangingtheresultinglogicfunction.(Figure6-69)(对于异或门、同或门的任何2个信号（输入或输出）都可以取反，而不改变结果的逻辑功能)F=ABABFABFABABFFF=A’B’F=(A’B)’F=(AB’)’I1I2I3I4INODDDaisy-ChainConnection

(菊花链式连接)I1I2I3I4IMINODDTreeStructure

(树状连接)CascadingXORGates(Figure6-70）9-bitOdd/EvenParityGenerator74x280

(9位奇偶校验发生器74x280)ABCDEFGHIEVENODD74x280Figure6-71Parity-CheckingApplications用于检测代码在传输和存储过程中是否出现差错AEVENODD74x280HIAEVENODD74x280HI发端收端DB[0:7]DB[0:7]ERROR发端保证有偶数个1收端ODD有效表示出错奇数EVEN6.9Comparator（比较器）ComparetwoBinarywordsandindicatewhethertheyareequalComparator:CheckiftwoBinarywordsareequal

(等值比较器：检验数值是否相等)MagnitudeComparator:Comparetheirmagnitude(Greaterthan,Equal,Lessthan)

(数值比较器：比较数值的大小（>,=,<）)ComparatorHowtobuilda1-bitComparator?

(如何构造1位等值比较器？？)——UseXOR(XNOR)ABDIFFABEQDIFF:differentEQ:equalDIFFA0B0A1B1A2B2A3B3给出足够的异或门和宽度足够的或门，可以搭建任意输入位数的等值比较器。HowtoBuildaN-bitComparator?必须每位都相等——并行比较——串行比较4位等值比较器Iterativecircuit（迭代电路）Iterative：重复的,反复的,[数]迭代的PICICOPOPICICOPOPICICOPOC0C1C2CnPO0PO1POn-1Primaryoutputs主输出PI0PI1PIn-1Primaryinputs主输入Boundaryinputs边界输入Boundaryoutputs边界输出Cascadingoutput级联输出AnIterativeComparatorXYCMPEQIEQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11XYCMPEQIEQOXYCMPEQIEQO——每位串行比较ABEQ迭代的方法可能节省费用，但速度慢用于级联的输入Figure6-77EQOEQIEQ_LABLT_LGT_L1-BitMagnitudeComparator

(一位数值比较器)①A>B（A=1,B=0）则A·B’=1可作为输出信号②A<B（A=0,B=1）则A’·B=1可作为输出信号③A=B，则A⊙B=1，可作为输出信号输出低电平有效EQ_L=A·B’+A’·B=AB=(A⊙B)’LT:LessThanEQ:EqualGT:GreaterThan(A’·B)’(A·B’)’n-BitMagnitudeComparator

(多位数值比较器)A(A3A2A1A0)

和

B(B3B2B1B0)自高而低逐位比较EQ=(A3⊙B3)·(A2⊙B2)·(A1⊙B1)·(A0⊙B0)GT=(A3>B3)LT=EQ’·GT’=(EQ+GT)’或(A3=

B3)·(A2=

B2)·

(A1>B1)或(A3=

B3)·(A2=

B2)·(A1=

B1)·

(A0>B0)或(A3=

B3)·

(A2>B2)A3·

B3’A2·

B2’A1·

B1’A0·

B0’⊙⊙⊙⊙⊙⊙+++74x854-BitComparator74x85

(4位比较器74x85)A0A1A2A3ALTBINAEQBINAGTBIN级联输入，用于扩展ALTBOUT=(A<B)+(A=B)·ALTBIN通常低位的输出接高位的输入A=B：低位和高位都相等A高位>B高位A高位=B高位&A低位>B低位A>BAEQBOUT=(A=B)·AEQBINAGTBOUT=(A>B)+(A=B)·AGTBINSerialExpandingComparators

(比较器的串行扩展)XD[11:0]YD[11:0][3:0][7:4][11:8]X<YX=YX>Y+5VA<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x853片74x85构成12位比较器低位高位P0P1P2P3P4P5P6P78-bitcomparator74x682问题1：怎样表示以下输出？

active-high：PDIFFQ

active-high：PEQQactive-high：PGEQ

active-high：PLTQ（P463图6-81）GELT问题2：能否扩展？？注意：没有级联输入端P464Figure6-823片74x682构成24位比较器P0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>Q[7:0][15:8][23:16]