半导体制造流程与IC产业链简介课件

IntroductiononFabflowandsemiconductorindustry--forITrelatedemployeeMorrisL.YehUMC.Fab8AB.PEI.Logic2IntroductiononFabflowandsOutline

1.FabflowandTransistorworking2.ICmanufacturingchain3.Filedapplication4.TheTrendOutline1.FabflowandTransiTheRoadmap

TheRoadmap1.1TransistorWorking1.What’stheTransistor?2.What’stheTransistorstructure?3.How’sthetransistorworking?4.TransistorandSystemrevolution3.1How’stheclockrunninginthetransistorring?3.2How’stheinformationbroadcastinginasystem?1.1TransistorWorking1.What’1.What’stheTransistor?TransistorWorkingInDigitalapplication,thetransistorplaytheroleofswitchinthesystemjustlikeamechanicalswitch,itmeansthatthekeycomponenttostoragethe0and1

State1State0ButwedeployedtheSolid-StateandQuantumphysicstorealizethesolid-stateswitch-Transistorinsiliconindustry,it’smoresizeshrinkage,highspeed,highperformanceandlowerenergyrequiredthanthepriorarts.State1State01.What’stheTransistor?Tran2.What’stheTransistorstructure?TransistorWorkingGateOxideUMC.Fab8B.Generic0.25umlogicTi-SalicideProcessPolyTiSi2SpacerSourceDrainChannelLengthLDDPOLYThetransistorincluded3terminalwhichlikestheswitch:1.PolyGateplaytheroleofcontrolorinputterminal,theDrainplaytheroleofoutputterminalandtheSourceplaytheroleofreferenceorground.2.What’stheTransistorstruc3.How’sthetransistorworking?TransistorWorkingState1DrainBias(charge)TimesLevel(V)State0GateBias(discharge)TimesLevel(V)State1DrainBias(recharge)TimesLevel(V)VoltageontheDrainterminal(output)=IntheDigitalapplication,thetransistorbehaviorsmorelikesaCapacitor:1.DrainBias(CapacitorCharge):ThechargestorageontheDrainside.2.GateBias(CapacitorDischarge):ThestoragechargeflowfromDraintoSource3.DrainBiasagain(Gatefloating,CapacitorRecharge):Thechargestorageagain.3.How’sthetransistorworkin3.1How’stheclockrunninginthetransistorring?Thevideoshownthe49stagesNOTgateserieswhichconstructedtheringoscillator,IntheleftNOTgatediagram,iftheinputterminalbecomestate0,thePMOSwasturnON,andNMOSturnedoff,itmeansthattheVccflowintoOutputterminal,theOutputstatebecome1,andaccordingquantumphysics,thecurrentflowthechannelmeansthatelectron-holepairrecombination,andthelightemissionwillbedetectedbythecooledinfraredcamera.TheRingOscillatorwasthetooltomeasurethesystemclockandspeed.GNDVccOutputInputPMOSNMOSNOTGateState0OnOffState1State1OffOnState03.1How’stheclockrunningin3.2How’stheinformationbroadcastinginasystem?Generally,there’safewpeoplecouldunderstoodtheinformationbroadcastinginachip,especiallyonthesystemdebug,theproductengineerhardtodetectthedefectinsystemlevel.Theliquid-nitrogen-cooledinfraredCameracoulddetectthehotspotemissionwhichgeneratedbytheelectron-holepaircombination.Thedefectcouldbedetectedoncethesignalflowtothedefectnode,thesystemwillbeholdandhotspotfrozenonthedefectnode.3.2How’stheinformationbroaFIG.1.Thefirsttransistor.BrattainandBardeen'spnppoint-contactgermaniumtransistoroperatedasaspeechamplifierwithapowergainof18onDecember23,1947.(BellLabs,Lucent)GateOxidePolyTiSi2SpacerSourceDrainChannelLengthFIG.3.TheworldwidesmallesttransistorGatelength0.061um.(BellLabs,Lucent)FIG.2.TheUMCpostgeneration0.25umstandardtransistor(UMC)4.1TheTransistorrevolutionTheFirstTransistor1947Belllabs.TheUMC0.25umTransistor1999,UMCTheworldwideleadship2001Belllabs.LucentFIG.1.Thefirsttransistor.DeviceIntegrationandTechnologydriveDeviceIntegrationandTechnol1.2Fabflow1.Lithographyconceptandcycle4.TransistorLayer(Front-end)definition5.RoutingLayer(Back-end)definition3.Modulecompositionandintegration2.Moduledefinition1.2Fabflow1.LithographyconLithographyconcept-physicalcyclePhotoResistCoatingMask&DUVStepperExposurePHOTOPhotoResistDevelopmentPHOTOEtching(Wet/Dry)PhotoResistStrippingETCHFilmDepositionRawmaterialThinFilmThinFilm-PHOTO-ETCHPhysicallayerformationcycleFabFlowLithographyconcept-physicalLithographyconcept-ImplantcyclePhotoResistCoatingMask&DUVStepperExposurePHOTOPhotoResistDevelopmentPHOTOFurnacefilmgrowthRawmaterialDiffusionIonImplantPhotoResistStrippingDiffusionDiffusion-PHOTO-DiffusionImplantlayercycleFabFlowLithographyconcept-Implant1.2Fabflow1.Lithographyconceptandcycle4.TransistorLayer(Front-end)definition5.RoutingLayer(Back-end)definition3.Modulecompositionandintegration2.Moduledefinition1.2Fabflow1.LithographyconPhoto:Rawmaterial:Reticle,PhotoResistEquipment:I-Line(MUV),DUV,EUV(Stepper,SCANNER)Vendors:Nikon,ASML2.Moduledefinition-PHOTOThePHOTOconceptwasgeneralOpticslithographytoreproducethespecificpatterns.TodaywedeployedtheUVExcimerlaserforthelight,AccordingtoOpticsprinciple,generallythewavelengthofthelightshouldbelessthanonetenthofhalfpitch,soifthetechnologyshrink,theExposurelightsourceshouldbepushedintodeeplyUVzone.Photo:2.Moduledefinition-PThin-Film:Rawmaterial:MetalTarget,ChemicalEquipment:Sputter,RTP,CVD(AP,PE,LP,SP,MO),ScubberVendors:AMAT,Novellus,TEL,ASM…..2.Moduledefinition-ThinFilmIngeneralwecansplittheThin-Filmintotwofield,oneisPhysicsdominated(PVD),theotherisChemicaldominated(CVD)ThePVDmeansthatnochemicalreactionassistedintheprocess,justsimplyacceleratedAratomtobombardthetargettoevaporatethetargetanddepositonthewafer,suchlikesSputter.TheCVDmeansthatthechemicalreactiononthewaferorchambertodepositafilmonthesurfaceCVDPVDChemicalreactionThin-Film:2.ModuledefinitionEtchRawmaterial:Solvent,ReactivegasEquipment:DryEtch(RIE),WetBench(ChemicalStation)Vendors:AMAT,Novellus,TEL,ASM…..2.Moduledefinition-ETCHIngeneralwecancallthatRIEinthetermofDryetching,thedryetchingwhichdominatedbythePhysicalIonbombardandchemicalreactionwiththesurfacetoevaporatedthebyproducts.ReactiveionbombardEtch2.Moduledefinition-ETCDiffusionRawmaterial:ChemicalGas,IsotopegasEquipment:Implanter,FurnaceVendors:Eaton,Varian,KE,TEL...2.Moduledefinition-DiffusionInthediffusion,there’retwomethodstodeliverthedopantintothesiliconwafer:.Implant:Toacceleratetheisotopeanddirectbombardthewafertodeliverthedopantintorightdepthwithrightconcentration..Furnace:Tousethermaldiffusionpotentialtodeliverthedopantintorightdepthwithrightconcentration.Diffusion2.ModuledefinitionCMPRawmaterial:Slurry,polishpadEquipment:CMP(W-CMP,Oxide-CMP,Cu-CMP)Vendors:AMAT,COBAT,Strasbaugh2.Moduledefinition-CMPIngeneral,theCMPlikethepolisharts,butdeployedthechemical-mechanicalassistant.There’retwofactorsdominatedtheCMPprocess:.Firstischemicalhydrolysisslurrytohydrolyzethesurface,.Secondistheslurryabrasivetoremovethehydrolytewhichunderthemechanicaldominated.CMP2.Moduledefinition-CMP1.2Fabflow1.Lithographyconceptandcycle4.TransistorLayer(Front-end)definition5.RoutingLayer(Back-end)definition3.Moduleintegration2.Moduledefinition1.2Fabflow1.LithographyconProcessFlowLayer(Route)Module(Step)3.ModuleintegrationProcessFlowLayer(Route)Modul1.2Fabflow1.Lithographyconceptandcycle4.TransistorLayer(Front-end)definition5.RoutingLayer(Back-end)definition3.Modulecompositionandintegration2.Moduledefinition1.2Fabflow1.LithographyconBriefProcessFlow-FirstLayer(Diffusion)P-sub(Siliconwafer)SiN(Nitrid)Padoxide1.1.WaferStart1.2.PADOxidation

110A(stressbuffer)1.7.SiN(Nitrid)Deposition1.5KA1.8.DiffusionLithography:1.8.1P.R.coating1.8.2StepperExposure1.8.3DevelopmentPhotoResistorcoatingDiffusionmaskStepperExposureDiffusionP.R.P-sub(Siliconwafer)SiN(Nitrid)PadoxideBriefProcessFlow-FirstLayDiffusionP.R.P-sub(Siliconwafer)SiN(Nitrid)PadoxideSTISTIBriefProcessFlow-FirstLayer(Diffusion)cont’1.7.Trench(STI)PlasmaEtching1.7.1SiNEtching1.7.2SiliconEtching1.8.PhotoResistorremoveDiffusionP.R.SiN(Nitrid)PadBriefProcessFlow-FirstLayer(Diffusion)cont’1.7.APCVDSTIrefill1.7.1LinerOxideGrowth1.7.2APCVDOxidedeposition1.7.3STIFurnace1000CDensify1.8.STICMP1.9.SiNremoveDiffusionP.R.P-sub(Siliconwafer)SiN(Nitrid)PadoxideSTISTISTIBriefProcessFlow-FirstLayN-WELLMaskBriefProcessFlow-WellformationP.R.CoatingN-WELLP.R.StepperExposure2.1N-WELLFormation:2.1.1N-WELLPRcoating2.1.2N-WELLLithography2.1.3Development2.1.4N-WELLimplant2.1.5PRstripping2.2P-WELLFormation:2.2.1P-WELLPRcoating2.2.2P-WELLLithography2.2.3Development2.2.4P-WELLimplant2.2.5PRstrippingP-sub(Silicon)Sac.oxideSTIPWELL

N-WELLP.R.CoatingP-WELLMaskStepperExposureN-WELLImplant1.N-WELL-12.N-WELL-27.PMOS-VT8.PMOSanti-punchP-WELLImplant1.P-WELL-12.P-WELL-27.NMOS-VT8.NMOSanti-punchN-WELLMaskBriefProcessFlowBriefProcessFlow-GateOxideandPOLYPRcoatingP-sub(Silicon)NWELLPWELLGateOxideTGMaskStepperExposureGateOxide2UPOLYgrowth3GateOxideFormation:3.1ThickGateOxideGrowth3.2PRcoating3.3TGLithography3.4Development3.5RCA-AWetetching3.6PRstripping3.7ThinGateOxideGrowth4.PolyGrowth4.1undope.POLYgrowth4.2N+POLYPRcoating4.3N+POLYLithography4.4Development4.5N+POLYimplantandPRStripPRCoatingN+POLYMaskN+POLYPRN+POLYimplantStepperExposureBriefProcessFlow-GateOxidBriefProcessFlow-GateEngineeringP-subNWELLSTIPWELLPolyPRcoatingPolyMaskNLDDN-LDDN-PKTN-LDDN-PKTP-LDDPR

P-LDDP-PKTStepperExposureN-LDDImplantP-LDDimplant5PolyGateFormation:5.1Polyannealing5.2PRcoating5.3POLYLithography5.4Development5.5POLYGateetching5.6PRstripping5.7ThinOxideGrowth6.LDD(LightDopeDrain)implant6.1N-LDDLithography(ellipsis)6.2NLDD/N-PKTimplant6.3P-LDDLithography(ellipsis)6.4PLDD/P-PKTimplantBriefProcessFlow-GateEngiBriefProcessFlow-DrainEngineeringP-subNWELLSTIPWELLPolyPRcoatingPolyMaskNLDDN-LDDN-PKTN-LDDN-PKTP-LDDPR

P-LDDP-PKTN+PRN+N+P+PRP+P+ImplantN+implantGateOxideUMC.Fab8B.Generic0.25umlogicTi-SalicideProcessPolyTiSi2SpacerSourceDrainChannelLength7PolyGateFormation:7.1Polyannealing7.2PRcoating7.3POLYLithography7.4Development7.5POLYGateetching7.6PRstripping7.7ThinOxideGrowth8.LDD(LightDopeDrain)implant8.1N-LDDLithography(ellipsis)8.2NLDD/N-PKTimplant8.3P-LDDLithography(ellipsis)8.4PLDD/P-PKTimplantBriefProcessFlow-DrainEng1.2Fabflow1.Lithographyconceptandcycle4.TransistorLayer(Front-end)definition5.RoutingLayer(Back-end)definition3.Modulecompositionandintegration2.Moduledefinition1.2Fabflow1.LithographyconBriefProcessFlow-ILDPassivationP-subNWELLSTIPWELLPolyPRcoatingPolyMaskNLDDN-LDDN-PKTN-LDDN-PKTP-LDDPR

P-LDDP-PKTN+PRN+N+P+PRP+SABPSGUSG9.SalicideFormation:9.1PETEOS-500ACapOxidedep.9.2SAB(Salicide-Block)Lithography(ellipsis)9.3Ti/Cosputtering9.4SalicidationRTPC49annealing9.5SalicidationRTPC54annealing9.6TiresidualSemi-toolwetclean10.ILDPassivation10.1SiN300Adeposition(Moistureandsodiumblock)10.2AP-USGdeposition(GapfillingandB,Ptrap)10.3TEOS-BPSG-14Kdeposition(re-flowandplanarization)10.4ILDCMPBriefProcessFlow-ILDPassiP-subNWELLSTIPWELLPolyPRcoatingPolyMaskNLDDN-LDDN-PKTN-LDDN-PKTP-LDDPR

P-LDDP-PKTN+PRN+N+P+PRP+SABPSGUSGPRCoatingBriefProcessFlow-ContactPlug

ContactMaskPRcoatingContactPRMetal1DUVStepperExposure11.ContactPlugFormation:11.1ContactLithography11.2ContactPlasmaEtching11.3PRstrip11.4Barrierlayerdeposition(Ti+TiNforwellcontact)11.5RTPannealing11.6GlueLayerdeposition(Ti+TiNforplugadhesion)11.5WCVDfilling11.6WCMP11.7MetalLinerdeposition(Ti+TiNforMetaladhesion)11.8MetalSputterP-subNWELLSTIPWELLPolyPRcoatiBriefProcessFlow-Backendroutine(Aluminumline)P-subNWELLSTIPWELLPolyPRcoatingPolyMaskNLDDN-LDDN-PKTN-LDDN-PKTP-LDDPR

P-LDDP-PKTN+PRN+N+P+PRP+SABPSGUSGPRCoating

ContactMaskPRcoatingContactPRMetal1ContactplugPRCoatingMetal1maskMetal1PRMetal1HDP-1PEOXCapOxidePRCoatingMVIA1maskMVIA1PRMetal2

StepperExposureStepperExposure12.IMDdeposition12.1HDP-Oxidedeposition(Gapfilling)12.2PE-OxideDeposition(Planarizationanduniformity)12.3IMDCMP12.4CapPE-Oxide13.MVIAplugformation13.1MVIALithographycycle13.2MVIAEtchingandPRstrip13.3GlueLayerdeposition(Ti+TiNforplugadhesion)13.4WCVDfilling13.5WCMP13.6MetalLinerdeposition(Ti+TiNforMetaladhesion)13.7MetalSputterBriefProcessFlow-BackendrBriefProcessFlow-AluminumlineMVIA1MVIA2MVIA3MVIA4MVIA5PassivationM5-8KM6-8KM4-5KM3-5KM2-5KM1-5KUMC.Fab8B.Generic0.25umlogicTi-SalicideProcessBriefProcessFlow-AluminumP-subNWELLSTIPWELLPolyPRcoatingPolyMaskNLDDN-LDDN-PKTN-LDDN-PKTP-LDDPR

P-LDDP-PKTN+PRN+N+P+PRP+SABPSGUSGContactplugBriefProcessFlow-Backendroutine(CopperDualDamascene)PRCoatingMetal1maskMetal1Metal2MaskStepperExposure2MVIA1MaskMetal2StepperExposure1StepperExposure314.ILD/M1Damascene14.1PEOX-3.6Kdeposition14.2M1Lithography14.3M1TrenchEtching14.4M1CuElectroplate(ECP)14.5CuCMP15.M2/MVIA1DualDamascene15.1PEOX-9Kdeposition15.2M2Lithography15.3M2TrenchEtching15.4MVIA1Lithography15.5MVIA1PlugEtching15.6TrenchLinerdeposition15.7M2/MVIA1CuECP15.8CuCMPP-subNWELLSTIPWELLPolyPRcoatiBriefProcessFlow-CopperDualDamasceneBriefProcessFlow-CopperDuComplexityAdvantageThehigherconductivityofcoppersimplifiesinterconnectrouting.Thisreducesthenumberofinterconnectlevelsfrom12to6,whichremovesupwardsof200processstepsandhasadirectimpactondeviceyield.PowerAdvantageChipswithcopperinterconnectwilloperatewithapproximately30%lesspoweratagivenfrequencythanchipswithaluminuminterconnect.Thistechnologywillenabledeviceswithsignificantlyhigherperformanceformobileapplications.CostAdvantage

Thesemiconductorindustryhashistoricallyreducedthecostperfunctionby25%to30%peryear.Thereductionincriticalprocessstepswiththedual-Damascenecopperprocessreducestheoverallcostby30%perinterconnectlevel.SpeedAdvantage

At0.13μm,theinterconnectdelayforcopperandlow-kmaterialsisapproximatelyone-halfthatofaluminumandSiO2.Copperisaclearchoiceat0.13μmandsmallerbecauseitprovidesspeedenhancementwithnosacrificeofdevicereliability.

WhyCopper?ComplexityPowerAdvantageCostDiffusionbarrier[SiN]IMD-Via[lowkOx]TrenchEtchingStop[SiN]IMD-Trench[LowkOx]HardMask[SiN]ARCLithography[SiON]TrenchfirstVialastEtchingCuBarrier[TaN]CuseedCVDCuECPCuCMPBriefProcessFlow-CopperDualDamasceneDiffusionbarrierIMD-ViaTrencOutline

1.FabflowandTransistorworking2.ICmanufacturingchain3.Filedapplication4.TheTrendOutline1.FabflowandTransiwaferprocessingFront-endLot/waferBack-endwaferSorting(C/Ptesting)C/P:CircuitprobingWafer/diceSystemDesignSynthesis,simulation,andphysicallayoutDesignMaskToolingDesigningstageReticle.gdsdBSystem2.ICmanufacturingchain-Front-endIDMFablessTurnkeyFundrywaferprocessingFront-endLot/wDiesawingWirebondSolderbumpedPackageFinalTestBurn-inBack-endWafer/diceDice/chipchipchipchipFieldApplicationmodule2.ICmanufacturingchain-BackendAssemblyandTestingIDMSystemHouseDiesawingWirebondPackageFinaICDesignflowSimulationandTestbilitydesignLevelDesignVerification,

Physicallayoutgeneration,designoptimization,TestpatterngenerationLevelTapeout,DRC,MaskToolingandFabPilotLevelSystemDesignEntryandAnalysisSystemSynthesisandTechnologyOptimizationLevelICDesignflowSimulationandBackendAssemblyflowWaferlevelDielevelChiplevelBackendAssemblyflowWaferlevICmanufacturingchain-Capital,cycleandgrossmarginDesignProductionTimeToMarket=0.5~0.75year(withoutqualification)ICmanufacturingchain-CapiOutline

1.FabflowandTransistorworking2.ICmanufacturingchain3.Filedapplication4.TheTrendOutline1.FabflowandTransi3.Filedapplication3.FiledapplicationOutline

1.FabflowandTransistorworking2.ICmanufacturingchain3.Filedapplication4.TheTrendOutline1.FabflowandTransiDeviceIntegrationandTechnologydriveDeviceIntegrationandTechnolNotes: (1) BoxCenterrepresentsstartatPilotProductionSchedule. (2) BasedonlogicandeSRAMroadmap. (3) SIA=SemiconductorIndustryAssociationUMC/SIATechnologyRoadMap19992000200120020.18µm0.15µmCu0.18µm0.13µmCu20032004SIA0.10µmCu0.07µmCu0.18µm0.13µmCu0.10µmCuUMCNotes: (1) BoxCenterrepresenTechnologyRoadMapNote:(1)BoxCenterrepresentsPilotProductionSchedulebegins.1998199920002001eDRAM0.35µm0.25µm0.18µmLogiceSRAMMixed-Mode/RF0.15µm0.25µm0.18µmEmbeddedFlashMemory0.35µm0.25µm0.13µm0.18µmCu0.15µm0.25µm0.18µm0.13µmCu0.18µmTechnologyRoadMapNote:(1)BHardwareandprocesslimitationThetwomajorlimitations:oneisGatehighkdielectricmaterial,theotherisGatelinewidthlimitation,itmeansthatbeyondDUVlightsourceshouldbedeveloped,andthecooperatingshouldbedevelopedwhichcontainedReticle,PhotoResist,Stepper,InspectionandMetrologytools.HardwareandprocesslimitatioGenerationandApplicationmix

*BasedonCurrentDemand/ForecastProjectionsUMCtechnologymixASETproductmixThere’retwosignificanttrendinthesetwofigures:Thetechnologywillbedrivenintodeepsub-microntechnology,andthePCdidn’tdominatethethefieldapplicationmix.GenerationandApplicationmixMorganStanley

:SemigrowthfollowsGDPmovement/Articles/Article_Display.cfm?Section=Archives&Subsection=Display&ARTICLE_ID=90573Meandmyshadow:SemigrowthfollowsGDPmovementUpwardorDownward?MorganStanley:Semigrowthf演讲完毕，谢谢观看！演讲完毕，谢谢观看！IntroductiononFabflowandsemiconductorindustry--forITrelatedemployeeMorrisL.YehUMC.Fab8AB.PEI.Logic2IntroductiononFabflowandsOutline

1.FabflowandTransistorworking2.ICmanufacturingchain3.Filedapplication4.TheTrendOutline1.FabflowandTransiTheRoadmap

TheRoadmap1.1TransistorWorking1.What’stheTransistor?2.What’stheTransistorstructure?3.How’sthetransistorworking?4.TransistorandSystemrevolution3.1How’stheclockrunninginthetransistorring?3.2How’stheinformationbroadcastinginasystem?1.1TransistorWorking1.What’1.What’stheTransistor?TransistorWorkingInDigitalapplication,thetransistorplaytheroleofswitchinthesystemjustlikeamechanicalswitch,itmeansthatthekeycomponenttostoragethe0and1

State1State0ButwedeployedtheSolid-StateandQuantumphysicstorealizethesolid-stateswitch-Transistorinsiliconindustry,it’smoresizeshrinkage,highspeed,highperformanceandlowerenergyrequiredthanthepriorarts.State1State01.What’stheTransistor?Tran2.What’stheTransistorstructure?TransistorWorkingGateOxideUMC.Fab8B.Generic0.25umlogicTi-SalicideProcessPolyTiSi2SpacerSourceDrainChannelLengthLDDPOLYThetransistorincluded3terminalwhichlikestheswitch:1.PolyGateplaytheroleofcontrolorinputterminal,theDrainplaytheroleofoutputterminalandtheSourceplaytheroleofreferenceorground.2.What’stheTransistorstruc3.How’sthetransistorworking?TransistorWorkingState1DrainBias(charge)TimesLevel(V)State0GateBias(discharge)TimesLevel(V)State1DrainBias(recharge)TimesLevel(V)VoltageontheDrainterminal(output)=IntheDigitalapplication,thetransistorbehaviorsmorelikesaCapacitor:1.DrainBias(CapacitorCharge):ThechargestorageontheDrainside.2.GateBias(CapacitorDischarge):ThestoragechargeflowfromDraintoSource3.DrainBiasagain(Gatefloating,CapacitorRecharge):Thechargestorageagain.3.How’sthetransistorworkin3.1How’stheclockrunninginthetransistorring?Thevideoshownthe49stagesNOTgateserieswhichconstructedtheringoscillator,IntheleftNOTgatediagram,iftheinputterminalbecomestate0,thePMOSwasturnON,andNMOSturnedoff,itmeansthattheVccflowintoOutputterminal,theOutputstatebecome1,andaccordingquantumphysics,thecurrentflowthechannelmeansthatelectron-holepairrecombination,andthelightemissionwillbedetectedbythecooledinfraredcamera.TheRingOscillatorwasthetooltomeasurethesystemclockandspeed.GNDVccOutputInputPMOSNMOSNOTGateState0OnOffState1State1OffOnState03.1How’stheclockrunningin3.2How’stheinformationbroadcastinginasystem?Generally,there’safewpeoplecouldunderstoodtheinformationbroadcastinginachip,especiallyonthesystemdebug,theproductengineerhardtodetectthedefectinsystemlevel.Theliquid-nitrogen-cooledinfraredCameracoulddetectthehotspotemissionwhichgeneratedbytheelectron-holepaircombination.Thedefectcouldbedetectedoncethesignalflowtothedefectnode,thesystemwillbeholdandhotspotfrozenonthedefectnode.3.2How’stheinformationbroaFIG.1.Thefirsttransistor.BrattainandBardeen'spnppoint-contactgermaniumtransistoroperatedasaspeechamplifierwithapowergainof18onDecember23,1947.(BellLabs,Lucent)GateOxidePolyTiSi2SpacerSourceDrainChannelLengthFIG.3.TheworldwidesmallesttransistorGatelength0.061um.(BellLabs,Lucent)FIG.2.TheUMCpostgeneration0.25umstandardtransistor(UMC)4.1TheTransistorrevolutionTheFirstTransistor1947Belllabs.TheUMC0.25umTransistor1999,UMCTheworldwideleadship2001Belllabs.LucentFIG.1.Thefirsttransistor.DeviceIntegrationandTechnologydriveDeviceIntegrationandTechnol1.2Fabflow1.Lithographyconceptandcycle4.TransistorLayer(Front-end)definition5.RoutingLayer(Back-end)definition3.Modulecompositionandintegration2.Moduledefinition1.2Fabflow1.LithographyconLithographyconcept-physicalcyclePhotoResistCoatingMask&DUVStepperExposurePHOTOPhotoResistDevelopmentPHOTOEtching(Wet/Dry)PhotoResistStrippingETCHFilmDepositionRawmaterialThinFilmThinFilm-PHOTO-ETCHPhysicallayerformationcycleFabFlowLithographyconcept-physicalLithographyconcept-ImplantcyclePhotoResistCoatingMask&DUVStepperExposurePHOTOPhotoResistDevelopmentPHOTOFurnacefilmgrowthRawmaterialDiffusionIonImplantPhotoResistStrippingDiffusionDiffusion-PHOTO-DiffusionImplantlayercycleFabFlowLithographyconcept-Implant1.2Fabflow1.Lithographyconceptandcycle4.TransistorLayer(Front-end)definition5.RoutingLayer(Back-end)definition3.Modulecompositionandintegration2.Moduledefinition1.2Fabflow1.LithographyconPhoto:Rawmaterial:Reticle,PhotoResistEquipment:I-Line(MUV),DUV,EUV(Stepper,SCANNER)Vendors:Nikon,ASML2.Moduledefinition-PHOTOThePHOTOconceptwasgeneralOpticslithographytoreproducethespecificpatterns.TodaywedeployedtheUVExcimerlaserforthelight,AccordingtoOpticsprinciple,generallythewavelengthofthelightshouldbelessthanonetenthofhalfpitch,soifthetechnologyshrink,theExposurelightsourceshouldbepushedintodeeplyUVzone.Photo:2.Moduledefinition-PThin-Film:Rawmaterial:MetalTarget,ChemicalEquipment:Sputter,RTP,CVD(AP,PE,LP,SP,MO),ScubberVendors:AMAT,Novellus,TEL,ASM…..2.Moduledefinition-ThinFilmIngeneralwecansplittheThin-Filmintotwofield,oneisPhysicsdominated(PVD),theotherisChemicaldominated(CVD)ThePVDmeansthatnochemicalreactionassistedintheprocess,justsimplyacceleratedAratomtobombardthetargettoevaporatethetargetanddepositonthewafer,suchlikesSputter.TheCVDmeansthatthechemicalreactiononthewaferorchambertodepositafilmonthesurfaceCVDPVDChemicalreactionThin-Film:2.ModuledefinitionEtchRawmaterial:Solvent,ReactivegasEquipment:DryEtch(RIE),WetBench(ChemicalStation)Vendors:AMAT,Novellus,TEL,ASM…..2.Moduledefinition-ETCHIngeneralwecancallthatRIEinthetermofDryetching,thedryetchingwhichdominatedbythePhysicalIonbombardandchemicalreactionwiththesurfacetoevaporatedthebyproducts.ReactiveionbombardEtch2.Moduledefinition-ETCDiffusionRawmaterial:ChemicalGas,IsotopegasEquipment:Implanter,FurnaceVendors:Eaton,Varian,KE,TEL...2.Moduledefinition-DiffusionInthediffusion,there’retwomethodstodeliverthedopantintothesiliconwafer:.Implant:Toacceleratetheisotopeanddirectbombardthewafertodeliverthedopantintorightdepthwithrightconcentration..Furnace:Tousethermaldiffusionpotentialtodeliverthedopantintorightdepthwithrightconcentration.Diffusion2.ModuledefinitionCMPRawmaterial:Slurry,polishpadEquipment:CMP(W-CMP,Oxide-CMP,Cu-CMP)Vendors:AMAT,COBAT,Strasbaugh2.Moduledefinition-CMPIngeneral,theCMPlikethepolisharts,butdeployedthechemical-mechanicalassistant.There’retwofactorsdominate