内嵌BRAM设计LIFO堆栈

.CLK2X180(),.CLK90(),.CLK180(),.CLK270(),丄OCKED(),.PSDONEO,.STATUS。)；endmoduleRTL图为图5.3.1 clkf倍频模块RTL图仿真代码为：moduleclk300m_tb;//Inputsregclk;regrst_p;//Outputswireclk_out;//InstantiatetheUnitUnderTest(UUT)clkfuut(.clk(clk),•rst_p(rst_p),.clk_out(clk_out)initialbegin//InitializeInputsclk=0;rst_p=0;//Wait100nsforglobalresettofinish#100;//Addstimulushereendalways#10clk=~clk;endmodule结果为：图5.3.1clkf倍频模块仿真因为clkfx_divide为1,clkfx_multiply为5,所以是倍频5倍,由图可看出刚好5倍，所以结果是对的。4、sf采样模块此模块是采样滤波，只要是为了消抖。//singalfiltermodulesf#(parametertimes= 20'b1111_0100_0010_0100_0000,//1000000width=20)(clk,rst_n,in,out);inputclk;inputrst_n;

inputin;outputout;regin_r1=1'b0;regin」2=1'b0;regin」3=1'b0;reg[width-1:0]filterp={width{1'b0}}; //posedgefilterwire[width-1:0]filterp_pre;always@(posedgeclkornegedgerst_n)if(!rst_n)beginin_r1<=1'b0;in_r2<=1'b0;in_r3<=1'b0;endelsebeginin_r1<=in;in_r2<=in_r1;in_r3<=in_r2;endalways@(posedgeclkornegedgerst_n)if(!rst_n)beginfilterp<={width{1'b0}};endelsebeginfilterp<=filterp_pre;endassignfilterp_pre=~in_r3?{width{1'b0}}:filterp+1'b1;filterp+1'b1;assignout=(filterp==times)?1'b1:1'b0;endmoduleRTL图：

sfrsfroutallLj图5.4.1RTL图仿真代码为：'timescale1ns/1ps//////////////////////////////////////////////////////////////////////////////////Company://Engineer:////CreateDate:17:00:3904/25/2016//DesignName:sf//ModuleName:D:/myclass/Digitalsystemintegrationtechnology/lab3_lifo/lifo3/sf_tb.v//ProjectName:lifo//TargetDevice://Toolversions://Description:////VerilogTestFixturecreatedbyISEformodule:sf////Dependencies:////Revision://Revision0.01-FileCreated//AdditionalComments://////////////////////////////////////////////////////////////////////////////////modulesf_tb;//Inputsregelk;regrst_n;regin;//Outputswireout;//InstantiatetheUnitUnderTest(UUT)sf#(.times(5),•width(10))uut(.elk(elk),.rst_n(rst_n),.in(in),.out(out));initialbegin//InitializeInputselk=0;rst_n=1;in=0;#1rst_n=0;#1rst_n=1;#200;repeat(12)begin#10in=1;#10in=0;end#300;repeat(12)begin#10in=1;#10in=0;end#10in=1;#300in=0;repeat(12)begin#10in=1;#10in=0;end//Wait100nsforglobalresettofinish#100;//Addstimulushereendalways#5elk=~clk;endmodule结果为图542仿真代码结果前面几段故意仿真不小心抖动一下按键，结果并不会产生信号，长按按键才会出现高电平。5、psp电平转脉冲模块modulepsp#(parameterwidth=2)(elk,rst_n,in,pulse)；inputelk;inputrst_n;input[width-1:0]in;output[width-1:0]pulse;reg[width-1:0]in_r1={width{1'b0}};reg[width-1:0]in_r2={width{1'b0}};always@(posedgeclkornegedgerst_n)if(!rst_n)beginin_r1<={width{1'b0}};

in_r2<={width{1'bO}};endelsebeginin_r1<=in;in_r2<=in_r1;endassignpulse=~in_r2&in_r1;图5.6.2RTL展开图endmoduleRTL图5.6.2RTL展开图图5.6.1RTL图仿真代码：modulepsp_tb;parameterwidth=3;//Inputsregelk;regrst_n;reg[width-1:0]in;//Outputswire[width-1:0]pulse;//InstantiatetheUnitUnderTest(UUT)psp#(width)uut(•clk(clk)..rst_n(rst_n)..in(in),.pulse(pulse))；initialbegin//InitializeInputsclk=0;rst_n=1;in=0;#1rst_n=0;#1rst_n=1;repeat(4)begin#40in=3'h1;#100in=3'h0;#40in=3'h2;#100in=3'h0;#40in=3'h4;#100in=3'h0;#40in=3'h7;#100in=3'h0;end//Wait100nsforglobalresettofinish#100;//Addstimulushereendalways#10clk=~clk;endmodule结果为:这是两个电平信号转换成相对应的脉冲信号，如结果所示，正确无误。6、spf脉冲时间拉长模块此模块是为了延长wr和rd的时间，从而在VGA上显示的时间足以让人们看到。//SignalPulseFiltermodulespf#(parametertimes=20'b1111_0100_0010_0100_0000, //1000000width=20)(elk,rst_n,in,out)；inputelk;inputrst_n;inputin;//signalinoutputout;//singnalregin_r1=1'b0;regin_r2=1'b0;regin_r3=1'b0;reg[width-1:0]filter={width{1'b0}};wire[width-1:0]filter_pre;regout_r=1'b0;wireout_pre;always@(posedgeelkornegedgerst_n)if(!rst_n)beginin_r1<=1'b0;in_r2<=1'b0;in_r3<=1'b0;endelsebeginin_r1<=in;in_r2<=in_r1;in_r3<=in_r2;endalways@(posedgeelkornegedgerst_n)if(!rst_n)filter<={width{1'b0}};elsefilter<=filter_pre;assignfilter_pre=in_r3?{width{1'b0}}:(filter==times)?filter:filter+1'b1;always@(posedgeclkornegedgerst_n)if(!rst_n)beginout_r<=1'b0;endelsebeginout_r<=out_pre;endassignout_pre=(filter==times)?in_r3:(out」|in_r3);assignout=out_r;endmoduleRTL图为：spfclkoutinrstn图5.6.1RTL图仿真代码为：modulespf_tb;//Inputsregelk;regrst_n;regin;//Outputswireout;//InstantiatetheUnitUnderTest(UUT)spf#(10)uut(.clk(clk),.rst_n(rst_n),.in(in),.out(out));initialbegin//InitializeInputsclk=0;rst_n=1;in=0;#1rst_n=0;#1rst_n=1;#18;#20in=1;#20in=0;//Wait100nsforglobalresettofinish#100;//Addstimulushereendalways#10clk=~clk;endmodule结果为：由图看可达到想要的结果。7、lifo模块此模块是控制RAM的读和写来实现lifo功能的modulelifo(clk,rst_n,wr,rd,din,full,empty,num,〃addr,wrdout,//writingdatarddout//readdata);inputclk;inputrst_n;inputwr;inputrd;input[3:0]din;output[3:0]num;output[3:0]wrdout;output[3:0]rddout;outputfull;outputempty;//output[3:0]addr;wire[3:0]addr;reg[4:0]cnt=5'h00;wire[4:0]cnt_pre;wire[3:0]ramdout;reg[3:0]rddout_r=4'h0;wire[3:0]rddout_pre;reg[3:0]wrdout_r=4'h0;wire[3:0]wrdout_pre;wirewe;wireen;parametermax=5'h09;always@(posedgeelkornegedgerst_n)if(!rst_n)ent<=5'h00;elseent<=ent_pre;assignent_pre=wr&!full?ent+1'b1:rd&!empty?ent-1'b1:ent;assignfull=(ent==max)?1'b1:1'b0;assignempty=(ent==5'h00)?1'b1:1'b0;assignaddr=empty?4'hO:ent_pre-1'b1;always@(posedgeelkornegedgerst_n)if(!rst_n)rddout_r<=4'h0;elserddout_r<=rddout_pre;assignrddout_pre=~rd?rddout_r:empty?4'hd:ramdout;assignrddout=rddout_r;always@(posedgeelkornegedgerst_n)if(!rst_n)wrdout_r<=4'h0;elsewrdout_r<=wrdout_pre;assignwrdout_pre=~wr?wrdout_r:full?4'hd:din;assignwrdout=wrdout_r;assignnum=cnt_pre[3:0];assignen=wr|rd;assignwe=wr&(!full);//bloekramIPram4x4u1ram4x4(.clka(clk),.ena(en),.wea(we),.addra(addr),.dina(din),.douta(ramdout))；endmodule8、video_signal_gen 时序产生模块在此模块中有输入有RGB，输出有横坐标X、纵坐标丫、行同步HS、场同步VS、使能DE、红色R值、绿色G值、蓝色B值。输入的RGB是为了给内部其他模块用的，可以根据输出的横坐标和纵坐标而改变屏幕的点的颜色。//Description :连接开发板的VGA接口和电脑液晶屏，// 即可显示640*480分辨率下的256种色彩modulevideo_signal_gen#（一一parameterHSTS=800, //allhsynctimesHSTDISP=640,//hsyncdisplaytimesHSTPW=:96,//hsyncplusewidthtimesHSTFP=16,//hsyncfrontplusetimesHSTBP=48,//hsyncbackplusetimesVSTS=521,//allvsyncplusetimesVSTDISP=480,//vsyncdisplayplusetimesVSTPW=:2,//vsyncplusetimesVSTFP=10,//vsyncfrontplusetimesVSTBP=29,//vsyncbackplusetimeswidth_x=10,//display x coordinatewidthwidth_y=10//display y coordinatewidth)(video_clk,rst_n,//raminterfacevideo_rgb,video_x,//pointcoordinatevideo_y,//VGAtransfervideo_hsync,video_vsync,video_de,video」video_g,video_b)；inputvideo_clk; //25MHzinputrst_n; //reset//raminterfaceinput[7:0]video_rgb;output[width_x-1:0]video_x;output[width_y-1:0]video_y;//FPGA与VGA接口信号outputvideo_hsync;// 行同步信号outputvideo_vsync;// 场同步信号outputvideo_de;//vaildoutput[2:0]video_r;output[2:0]video_g;output[1:0]video_b;// //coordinatecountreg[width_x-1:0]x_cnt; //行坐标wire[width_x-1:0]x_cnt_pre;reg[width_y-1:0]y_cnt; //列坐标wire[width_y-1:0]y_cnt_pre;//generatex_cntalways@(posedgevideo_clkornegedgerst_n)if(!rst_n)x_cnt<={width_x{1'b0}};elsex_cnt<=x_cnt_pre;assignx_cnt_pre=(x_cnt==HSTS-1'b1)?{width_x{1'b0}}:(x_cnt+1'b1);//generatey_cntalways@(posedgevideo_clkornegedgerst_n)

if(!rst_n)y_cnt<={width_y{1'bO}};elsey_cnt<=y_cnt_pre;assigny_cnt_pre=(y_cnt==VSTS -1'b1)?{width_y{1'bO}}:((x_cnt==HSTS-1'b1)?(y_cnt+1'b1):y_cnt);//generatehsyncreghsync_r;wirehsync_r_pre;always@(posedgevideo_clkornegedgerst_n)if(!rst_n)hsync_r<=1'b1;elsehsync_r<=hsync_r_pre;assignhsync_r_pre=(x_cnt=={width_x{1'b0}})((x_cnt==HSTPW)?1'b1:hsync_r);assignvideo_hsync=hsync_r;//generatevsyncregvsync_r;wirevsync_r_pre;always@(posedgevideo_clkornegedgerst_n)if(!rst_n)vsync_r<=1'b1;elsevsync_r<=vsync_r_pre;assign vsync_r_pre=(y_cnt =={width_y{1'b0}})((y_cnt==VSTPW)?1'b1:vsync_r);assignvideo_vsync=vsync_r;//generatedevalidwirevideo_de;wirehs_de;wirevs_de;assignhs_de=(x_cnt>=HSTPW+HSTBP)&(x_cnt<HSTPW+HSTBP+HSTDISP);1'bO1'bOassignvs_de=(y_cnt>=VSTPW+VSTBP)&(y_cnt<VSTPW+VSTBP+VSTDISP);

1'bO1'bOassignvideo_de=hs_de&vs_de;//generatepointcoordinate(x,y)assignvideo_x=hs_de?(x_cnt-HSTPW-HSTBP+1'b1){width_x{1'b0}};assignvideo_y=vs_de?(y_cnt-VSTPW-VSTBP){width_y{1'b0}};//r,g,b控制液晶屏颜色显示assignvideo」=video_de?video_rgb[7:5]:3'b000;assignvideo_g=video_de?video_rgb[4:2]:3'b000;assignvideo_b=video_de?video_rgb[1:0]:2'b00;endmodule口HET展开图video_signal_gen1F 2]bd0)rajivrJoog(20)口HET展开图video_signal_gen1F 2]bd0)rajivrJoog(20)v*jeo_r(2:0}videojieVdi!O_Clk1k Hb2v_inst1图5.4.1video_signal_gen测试代码为modulevga256_tb;//Inputsregclock;regrst_p;〃Outputswirevsync;wirehsync;wirevga_de;

wire[1:0]vga_b;wire[2:0]vga_g;wire[2:0]vga_r;//InstantiatetheUnitUnderTest(UUT)vga256uut(.clock(clock),•rst_p(rst_p),.vsync(vsync),.hsync(hsync),•vga_de(vga_de),•vga_b(vga_b),•vga_g(vga_g),•vga_r(vga_r));initialbegin//InitializeInputsclock=0;rst_p=0;〃rst_n=1;#1rst_p=1;#1rst_p=0;//Wait100nsforglobalresettofinish#100;//Addstimulushereendalways#5clock=~clock;endmodule测试结果：gaidM.dL1bn«_™■・・*|_叫宰MIlWlu*lilM4kigaidM.dL1bn«_™■・・*|_叫宰MIlWlu*lilM4kiLlSESSS^':—e冈占同回］ rf图542测试结果1之前本人有根据上面的时间计算过，确实是一个 hs周期里有800个时钟，一个vs周期里有525个时钟，所以大胆猜测是对的，烧到板子上果然是对的。9、disp_alg模块此模块是算法，实现的是 Write和Read字的提取和动，还有方框的实现。由于单单看时序时是很难看出哪里错的，所以就不仿真了。moduledisp_alg#(parameterwidth_x=4'd10,width_y=4'd10,HSTDISP=10'd640,//hsync displaytimesVSTDISP=10'd480,//vsync displayplusetimeswrite_x_width =10'd266,write_y_width =10'd84,TOC\o"1-5"\h\zwrite_x_addrbase = (HSTDISP -write_x_width)/2,write_y_addrbase = (VSTDISP -write_y_width)/2,read_x_width =10'd252,read_y_width =10'd96,read_x_addrbase =(HSTDISP -read_x_width)/2,read_y_addrbase =(VSTDISP -read_y_width)/2)(clk_25m,clk2,rst_n,wr_rd_rst_n,wr,rd,vga_x,vga_y,

);vga_rgbinputclk_25m;inputclk2;inputrst_n;inputwr_rd_rst_n;inputwr;inputrd;input[width_x-1:0]vga_x;input[width_y-1:0]vga_y;output[7:0]vga_rgb;wirewr_en;//readWriteromenablewire[14:0]wr_addr;wirerd_en;//readReadromenablewire[14:0]rd_addr;wirewrrden;//readthewriteorreadworldenablewirewr_rgb;//readWiteromdatawirerd_rgb;//readReadromdatawire[7:0]rom_rgb;//readtheromdatawire[7:0]vga_rgb;wire[2:0]change_size;//displayworldsizereg[2:0]class=3'h0;wire[2:0]class_pre;regdirection=1'b0;//whenthenworldgettominimumormaximum,theworldwouldchangedirectionwiredirection_pre;regdirection2=1'b0;//whentheposedgedirectionarrival,directionwouldchangewiredirection2_pre;wire[8:0]offset_x;//theworldsizeoffsetoriginalsize(1:1)wire[9:0]vga_x;wire[9:0]vga_y;wire[14:0]x_addrmid;wire[14:0]x_addrleft;wire[14:0]x_addrlast;wire[14:0]x_addrright;wire[14:0]x_width;wire[14:0]y_width;wire[14:0]y_addrup;wire[14:0]y_addrdown;wire[14:0]addr_pose;wire[14:0]addr_nege;wire[14:0]addr;wire[7:0]datacolor;wire[7:0]wrframergb;wire[7:0]rdframergb;wire[7:0]numframergb;always@(posedgeclk2ornegedgewr_rd_rst_n)if(!wr_rd_rst_n)class<=3'h0;elseclass<=class_pre;assignclass_pre=direction?class-3'h1:class+3'h1;always@(posedgeclk2ornegedgewr_rd_rst_n)if(!wr_rd_rst_n)direction<=1'b0;elsedirection<=direction_pre;assigndirection_pre=(class_pre==3'h0)||(class_pre==3'h2)?~direction:direction;always@(posedgeclk2ornegedgewr_rd_rst_n)if(!wr_rd_rst_n)direction2<=1'b0;elsedirection2<=direction2_pre;assigndirection2_pre=(class_pre==3'h2)?~direction2:direction2;assignxwidth =wr?writexwidth:readxwidth;assigny_width =wr?write_y_width:read_y_width;parametermultiple=9'h100;〃256assignoffset_x=class==2'h0?x__width/2://*128/multiple:class===2'h1?x_width/4://*64 /multiple:class===2'h2?x_width/8:〃*32 /multiple:class===2'h3?x_width/16://*16 /multiple:x_width/32;//* 8multiple:assignchange_size=class==2'hO?1:〃multiple/256: 〃2 multiplechange_sizeclass==2'h1?2://multiple/128:TOC\o"1-5"\h\zclass==2'h2?4:〃multiple/64 :class==2'h3?8:〃multiple/32 :16;〃multiple/16 :assignx_addrmid=wr?write_x_addrbase+write_x_width/2read_x_addrbase+read_x_width/2;assignx_addrleft=x_addrmid-offset_x;assignx_addrlast=x_addrmid*change_size-x_width/2;assignx_addrright=x_addrmid+offset_x;assigny_addrup=wr?write_y_addrbase:read_y_addrbase;assigny_addrdown=y_addrup+y_width;assignwrrden =(vga_x>x_addrleft)&&(vga_x<=x_addrright)&&(vga_y>y_addrup)&&(vga_y<=y_addrdown)&&(wr||rd);assignaddr_pose=wrrden?((vga_x-1'b1)*change_size-x_addrlast)*y_width+vga_y-y_addrup:15'h0000;assignaddr_nege=wrrden?(x_width-((vga_x-1'b1)*change_size-x_addrlast))*y_width+vga_y-y_addrup:15'h0000;assignaddr =direction2?addr_nege:addr_pose;assigndatacolor=(vga_x-x_addrleft)*change_size;frame粼.x_lengthframe(8'd55),.y_lengthframe(8'd70),.x_frame(4'd10),.y_frame(4'd10))wrframe(.clk(clk_25m),.rst_n(rst_n),•vga_x(vga_x),•vga_y(vga_y),.frame_rgb(wrframergb));frame粼.x_lengthframe(8'd55),.y_lengthframe(8'd70),.x_frame(10'd575),.y_frame(4'd10))rdframe(.clk(clk_25m),.rst_n(rst_n),•vga_x(vga_x),•vga_y(vga_y),.frame_rgb(rdframergb));frame粼.x_lengthframe(8'd55),.y_lengthframe(8'd70),.x_frame(10'd278),.y_frame(4'd10))numframe(.clk(clk_25m),.rst_n(rst_n),•vga_x(vga_x),•vga_y(vga_y),.frame_rgb(numframergb));Write266x84u1writerom(.clka(clk_25m),.ena(1'b1),.addra(addr),.douta(wr_rgb));Read252x96u1readrom(.clka(clk_25m),.ena(1'b1),.addra(addr),.douta(rd_rgb));assignrom_rgb=~wrrden?8'b111_111_11:wr?(~wr_rgb?datacolor:8'b111_111_11):rd?(~rd_rgb?datacolor:8'b111_111_11):8'b111_111_11;assignvga_rgb=rom_rgb&wrframergb&rdframergb&numframergb;endmoduleRTL图：disp_algF~~ —1wsfBCB- ITOa_^b(7;Q>u1_alg图5.5.1disp_algRTL图5、disp_alg2模块此算法是在显示屏上显示读的数据、 RAM中的个数和写的数据。moduledisp_alg2#(parameterwidth_x=4'd10,width_y =4'd10,wrdataeolor=:8'b111_001_01,rddataeolor=8'b111_001_01,numdataeolor=8'b111_001_01,wrdata_x=10'd20,wrdata_y=10'd20,rddata_x=10'd585,rddata_y=10'd20,numdata_x=10'd288,numdata_y=10'd20,worldwidthx:=9'd35,worldwidthy:=9'd50,worldallpoint=12'd1750)(elk,rst_n,wrdata,rddata,numdata,vga_x,vga_y,vga_rgb)；inputelk;inputrst_n;input[3:0]wrdata;input[3:0]rddata;input[3:0]numdata;input[width_x-1:0]vga_x;input[width_y-1:0]vga_y;output[7:0]vga_rgb;wireenrom;//wireenwr;//theenableofwritewireenrd;//theenableofreadwireennum;regenwrbuf;regenrdbuf;regennumbuf;wire[3:0]data;wire[width_x-1:0]data_x;wire[width_y-1:0]data_y;assignenwr=(vga_x>=wrdata_x)&&(vga_x<wrdata_x+worldwidthx)&&(vga_y>=wrdata_y)&&(vga_y<wrdata_y+worldwidthy);assignenrd=(vga_x>=rddata_x)&&(vga_x<rddata_x+worldwidthx)&&(vga_y>=rddata_y)&&(vga_y<rddata_y+worldwidthy);assignennum=(vga_x>=numdata_x)&&(vga_x<numdata_xworldwidthx)&&(vga_y>=numdata_y)&&(vga_y<numdata_y+worldwidthy);assignenrom=enwr|enrd|ennum;always@(posedgeclkornegedgerst_n)if(!rst_n)beginenwrbuf<=1'b0;enrdbuf<=1'b0;ennumbuf<=1'b0;endelsebeginenwrbuf<=enwr;enrdbuf<=enrd;ennumbuf<=ennum;endassigndata=enwr?wrdataenrd?rddata:ennum?numdata:4'hd;assigndata_x=enwr?wrdata_x:enrd?rddata_x:ennum?numdata_x:10'hfff;assigndata_y=enwr?wrdata_y:enrd?rddata_y:ennum?numdata_y:10'hfff;assignromaddr=(vga_x+1'b1-data_x)*worldwidthy+vga_y-data_y+worldallpoint*data;assignvga_rgb=(data>4'hb)?8'b111_111_11:enwrbuf ?(romrgb?8'b111_111_11wrdatacolor):enrdbuf ?(romrgb?8'b111__111__11rddatacolor):ennumbuf?(romrgb?8'b111__111__11numdatacolor):8'b111_111_11;romnumromwnum(.clka(clk),.ena(enrom),.addra(romaddr),.douta(romrgb));endmodule六、报告资源报告：综合后的资源报告:实现后的资源报告:Oavi4?a Iffi1.i.-arataon. £口mim-a.Tj^~1~口L”iuVilli «nUsedonWulc(门NimherofSl-ieaFlipFlaps1729,3121%iTijinb^rof4